The era of low power microelectronics began with the invention of the transistor in the late 1940's and came of age with the invention of the integrated circuit in the late 1950's. Historically, the most demanding applications of low power microelectronics have been battery operated products such as wrist watches, hearing aids, implantable cardiac pacemakers, pocket calculators, pagers, cellular telephones and prospectively the hand-held multi-media terminal However, in the early 1990's low power microelectronics rapidly evolved from a substantial tributary to the mainstream of microelectronics. The principal reasons for this transformation were the increasing packing density of transistors and increasing clock frequencies of CMOS microchips pushing heat removal and power distribution to the forefront of the problems confronting the advance of microelectronics. The distinctive thesis of this discussion is that future opportunities for low power gigascale integration (GSI) will be governed by a hierarchy of theoretical and practical limits whose levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit, and (5) system. >

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Low power microelectronics: retrospect and prospect

It is shown that the influence of the drain-source field on the potential barrier height is physically equivalent to and can be replaced by a reduction in channel doping concentration according to a formula derived from the two-dimensional Poisson equation. The actual barrier height for any drain bias and channel length, on which the derived equation depends, can be calculated easily using well-known one-dimensional (long-channel) solutions. This simple but general procedure, called the voltage-doping transformation (VDT), is shown to lead to analytically calculated potential distributions in fairly good agreement with two-dimensional numerical simulation. An application of the VDT to threshold voltage (V/sub tj/) calculations also is shown. The V/sub th/ model is compared with measurements taken on implanted n-MOSFETs with various channel lengths. Good agreement demonstrates the accuracy of both the VDT and the new V/sub th/ model. >

The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects

This paper surveys, reviews, and critiques analytic models of MOSFET short-channel effects (SCEs) in subthreshold published over the past four decades. In the first half of this paper, the published models on SCEs are categorized into the following four main groups based on their approach: 1) charging sharing models; 2) empirical expressions; 3) polynomial potential models; and 4) analytic solutions to 2-D Poisson's equation. The strength and weakness of each approach are elaborated in terms of its physical soundness and predictive ability. A key development was the exponential dependence of SCE on channel length (L) , SCE ~ exp(-L/l0), leading to the introduction of scale length (l0). In the second half of this paper, the predictions of each analytic SCE model are examined by generic 2-D numerical simulations. In particular, the merit of each model is judged by its prediction on the scale length (l0) as a function of the thickness and dielectric constant (κ) of the gate insulator. Only one model, i.e., the generalized scale length model that treated the silicon and insulator regions as two distinct dielectric regions with shared boundary conditions, correctly predicted the MOSFET scale length under all dielectric constant and thickness conditions. A variation of the generalized scale length model applies to recent multiple-gate MOSFETs near the limit of scaling.

Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold

This is the first book dedicated to the next generation of MOSFET models. Addressed to circuit designers with an in-depth treatment that appeals to device specialists, the book presents a fresh view of compact modeling, having completely abandoned the regional modeling approach.

Mosfet Modeling for Circuit Analysis and Design

In this letter, we report a new approach to treat the 2-D nonlinear Poisson's equation in the context of MOS devices and discuss its application in the modeling of tunneling field-effect transistors (T-FET). It is revealed that the narrowing of tunneling barrier in T-FET has different mechanisms before and after inversion layer is formed. Closed-form equation is obtained to describe the barrier narrowing in the presence of inversion layer.

A Variational Approach to the Two-Dimensional Nonlinear Poisson's Equation for the Modeling of Tunneling Transistors

A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.

K.N. Ratnakumar

Papers

Short-channel MOST threshold voltage model