Introducing mobility to Wireless Sensor Networks (WSNs) puts new challenges particularly in designing of routing protocols. Mobility can be applied to the sensor nodes and/or the sink node in the network. Many routing protocols have been developed to support the mobility of WSNs. These protocols are divided depending on the routing structure into hierarchical-based, flat-based, and location-based routing protocols. However, the hierarchical-based routing protocols outperform the other routing types in saving energy, scalability, and extending lifetime of Mobile WSNs (MWSNs). Selecting an appropriate hierarchical routing protocol for specific applications is an important and difficult task. Therefore, this paper focuses on reviewing some of the recently hierarchical-based routing protocols that are developed in the last five years for MWSNs. This survey divides the hierarchical-based routing protocols into two broad groups, namely, classical-based and optimized-based routing protocols. Also, we present a detailed classification of the reviewed protocols according to the routing approach, control manner, mobile element, mobility pattern, network architecture, clustering attributes, protocol operation, path establishment, communication paradigm, energy model, protocol objectives, and applications. Moreover, a comparison between the reviewed protocols is investigated in this survey depending on delay, network size, energy-efficiency, and scalability while mentioning the advantages and drawbacks of each protocol. Finally, we summarize and conclude the paper with future directions.

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A Comprehensive Survey on Hierarchical-Based Routing Protocols for Mobile Wireless Sensor Networks: Review, Taxonomy, and Future Directions

A program-based anomaly intrusion detection scheme using multiple detection engines and fuzzy inference

Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays...

Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

Control flow-based opcode behavior analysis for Malware detection

Conventional digital circuits lose energy because the bits of information are destroyed during the operation. Reversible circuits are currently on the top approaches to power minimization with its application in all-optical-based systems. Fredkin gate is a very common reversible logic gate. In this paper, a modification of the Fredkin gate is proposed. All-optical circuit of this modified Fredkin gate (MFG) is also designed using semiconductor optical amplifier on the Mach-Zehnder interferometer switch. A 16-Boolean logical operational circuit is also shown using this MFG. The main advantage of this scheme is that we can design a 15-Boolean logical function using a single MFG unit. Only one operation (nand) required two MFG units. Hence, complexity of the circuit can be reduced. Also, multivalued T-gate circuit using MFG is proposed.

All-Optical Modified Fredkin Gate

In wireless sensor networks, the routing algorithms currently available assume that the sensor nodes are stationary Therefore when mobility modulation is applied to the wireless sensor networks, most of the current routing algorithms suffer from performance degradation The path breaks in mobile wireless networks are due to the movement of mobile nodes, node failure, channel fading and shadowing It is desirable to deal with dynamic topology changes with optimal effort in terms of resource and channel utilization As the nodes in wireless sensor medium make use of wireless broadcast to communicate, it is possible to make use of neighboring node information to recover from path failure Cooperation among the neighboring nodes plays an important role in the context of routing among the mobile nodes This paper proposes an enhancement to an existing protocol for accommodating node mobility through neighboring node information while keeping the utilization of resources to a minimum

/pdf/routing-protocol-enhancement-for-handling-node-mobility-in-1bruthwzf6.pdf

Routing protocol enhancement for handling node mobility in wireless sensor networks

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 times 4 multiplication, 64 combinations need 3 times 3 multiplication, and the remaining 32 combinations use either 3 times 4 or 4 times 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation of partial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit times n-digit) multiplication.

/pdf/decimal-multiplication-using-compact-bcd-multiplier-59r4oymch1.pdf

Decimal multiplication using compact BCD multiplier

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction - double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4times4 reversible gate called 'HCG' for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.

https://dyuthi.cusat.ac.in/xmlui/bitstream/handle/purl/3859/Fault%20Tolerant%20Error%20Coding%20and%20Detection%20using.pdf;sequence=1

Fault tolerant error coding and detection using reversible gates

This paper presents performance analysis of Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional fitter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in low-power consumption. RNS is a non-weighted number system without carry propagation between different residue digits. This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in RNS domain. Such compact and high speed real-time digital filters find applications in radar, communications and image processing systems.

/pdf/performance-analysis-of-fir-digital-filter-design-rns-versus-4f2xtolmag.pdf

Performance analysis of FIR digital filter design: RNS versus traditional

Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The design reduces the number of gates and garbage outputs compared to the existing BCD adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay.

/pdf/a-new-look-at-reversible-logic-implementation-of-decimal-csszulpiav.pdf

K.P. Jacob

Papers

Routing protocol enhancement for handling node mobility in wireless sensor networks

Decimal multiplication using compact BCD multiplier

Fault tolerant error coding and detection using reversible gates

Performance analysis of FIR digital filter design: RNS versus traditional

A New Look at Reversible Logic Implementation of Decimal Adder