Corrosion control in electronics and know-how concerning various protection methods have become an important field of design since electronics is increasingly used as integrated into different devices in highly corrosive conditions. On the other hand, the increase of the packaging density of electronics has resulted in electronics that is sensitive to the corrosive effects of the environment even in milder conditions. The project charted the mechanisms through which the climate, humidity, contamination, other environmental factors, the way of use of the device and its structure as well as the manufacturing process affect the corroding and faults of the electronics. A method was developed for solving these problems by which both the experienced and the beginning designer can check the feasibility of the applied corrosion protection technique and foresee possible corrosion problems in the structure of the device as well as find new approaches for solving them. The report also presents an evaluation method for the corrosive effect of the usage environment. In addition, various types of corrosion mechanisms and protection against them are described, corrosion analysis and measurement methods introduced and testing methods used for quality assurance regarding corrosion discussed. Comprehensive lists of standards and literature concerning corrosion and climatic effects are appended to the report. This report is available in English and in Finnish (VTT Publications 623, http://virtual.vtt.fi/inf/pdf/publications/2007/P623.pdf)

Corrosion and climatic effects in electronics

The chip/package I/Os count has continuously been growing as the systems become more complicated. High density I/Os interconnection and efficient escape routing with high performance and low cost will greatly benefit the whole electronic system. We analyze the properties of the hexagonal array, which can hold about 15% more I/Os compared with the traditional square grid array. We propose three escape routing strategies for the hexagonal array: column-by-column horizontal escape routing, two-sided horizontal/vertical escape routing, and multi-direction hybrid channel escape routing. We can escape I/Os in the hexagonal array in the same or less number of routing layers compared with square grid array. The practical examples show the efficiency of our strategies. Using hexagonal array, we can reduce the number of escape routing layers as well as increase the density of I/Os.

Efficient escape routing for hexagonal array of high density I/Os

will goonto boards with upto50layers. Newtechnologies, such as Thechip/package I/Os count hascontinuously beengrowing asthe flip chip, CSP,BGA,etc., aredeveloped forchip-level (first-level) systemsbecomemore complicated. Highdensity I/Os and package-to-board (second-level) interconnections to interconnection andefficient escape routing withhigh performance accommodate theincreasing demandofhighI/Osignals count. Area andlowcost will greatly benefit thewhole electronic system. We array interconnection iswidely usedinthose advanced technologies. analyze theproperties ofthehexagonal array, which canhold about Inorder toconnect theI/O signals inthearray tothenextlevel 15%moreI/Os compared withthetraditional square grid array. We assembly, wires arerouted tobreak I/Osignals outwhichisreferred propose three escape routing strategies forthehexagonal array: as"escape routing" [8][3][5]. column-by-column horizontal escaperouting, two-sided ThehighI/Osignals count anddensity require anincrease in horizontal/vertical escape routing, andmulti-direction hybrid thenumber ofescape routing layers andmakethesignal integrity channel escape routing. We canescape I/Os inthehexagonal array issue moreserious. An efficient andeffective escape routing inthesameorless number ofrouting layers compared with square strategy which achieves high performance with lowcost will greatly gridarray. Thepractical examples showtheefficiency ofour benefit theelectronic product. strategies. Using hexagonal array, wecanreduce thenumber of escape routing layers aswell asincrease thedensity ofFOs. Traditionally, theareaarray isasquare grid andI/Osignals are escaped row-by-row (column-by-column)

Efficient Escape Routing forHexagonal Array ofHighDensity I/Os

High density multilayer substrate technologies are indispensable to accommodate high input/outputs (I/Os) fine pitch area array integrated circuits (ICs), chip scale packages/ball grid arrays (CSP/BGAs) in the coming packaging generation. They must provide not only a high wiring density, but also an acceptable low cost, short turn around time (TAT) and reliability. Reduction of the number of layers is expected to be a reasonable solution for the conflicting demands. General approaches to reduce the layer count have been to decrease the size of the routing line width and spacing. However, they need changes in the manufacturing processes and materials, causing an increased cost. From escape routing design viewpoint, effects of routing manner on the layer count have been studied. A preferential routing creates specific pad geometry resulting in a high wiring efficiency. This effect can be estimated with an increase in the number of lines per layer routable as a contribution of "the hybrid channel," depending on capture pad pitch-pad diameter-line width-interline space relationship. It is one of the remarkable cases recognized that, within one line per channel rule, the preferential routing can be almost equivalent to that by two lines per channel with regard to the wireability. Its better effect on cost and TAT can also be expected compared with the two thinner sized lines per channel rule, since nothing changes in both manufacturing processes and materials is needed. This method is applicable immediately to packages and boards for assembly of the high I/O flip chips, CSPs, and BGAs.

Escape routing design to reduce the number of layers in area array packaging

Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al/sub 2/O/sub 3//AlN). New package or board materials with low CTE and high elastic modulus are needed for the next generation of high-performance convergent Microsystems to be able to fabricate ultra high-density wiring without big capture pads and to assemble area-array flip-chips with minimal stress on solder joint or perhaps completely eliminate underfills around the solder joint. A novel manufacturing process has been demonstrated to yield large-area thin carbon-silicon carbide (C-SiC) based composite boards with potentially low cost and desired thermomechanical properties - ultra high modulus, Si-matched CTE and large-area manufacturability. The reliability performance of this material was evaluated with flip chip test vehicle using conventional epoxies and advanced dielectrics such as BCB and PPE. Bumped dies were assembled and liquid-liquid thermal shock tests and Shadow Moire measurements were carried out to assess the solder joint reliability of these boards. In parallel with experiments, numerical models were also developed to analyze warpage, dielectric cracking and solder fatigue failure, and provide design guidelines. Though boards with Si-matched CTE are essential to lower the solder joint strains, they result in a high CTE mismatch between the build-up dielectrics and board, generating higher stresses in the dielectric which could lead to cracking. In this work, we show that dielectric cracking can be minimized with stiffer boards and thinner build-up layers. Based on the results, it can be inferred that high board stiffness and low CTE (/spl sim/3-4 ppm//spl deg/C) are needed to ensure reliability of high-density packages without the use of underfill. The test vehicle evaluation supported by modeling results indicate that the novel low-cost large-area processable ceramic matrix composite (C-SiC) has potential to be a promising candidate substrate material for next-generation microsystems.

Next generation of package/board materials technology for ultra-high density wiring and fine-pitch reliable interconnection assembly

Flip-chip and chip-scale packaging can increase the packaging density for integrated circuits on printed wiring boards and multichip modules. However, these approaches can result in I/O configurations that exceed the routing capabilities of the underlying board. We have examined the I/O density requirements of a wide variety of integrated circuit types. Simple linear ICs and gates are at one extreme, with few I/O and small area, and high-end microprocessors are at the other, with many I/O and large area. We analyze a representative routing escape strategy for area-array I/O, and use this analysis to determine the packaging limits of several different board technologies. Comparing these limits to the I/O configurations of various ICs in flip-chip and chip scale packages, we identify some classes of circuits (e.g., memory) that are more readily suited to conventional boards, and others (e.g., high end microprocessors) that will require very aggressive board technologies. We show that a successful overall packaging strategy will balance that need for high density chip packaging and smaller boards against the demands that these packages will make on the routing capabilities and cost per unit area of printed wiring boards.

K.V. Guinn

Papers

Flip-chip and chip-scale I/O density requirements and printed wiring board capabilities