This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

This paper describes design techniques to maximize the efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages). These methods are verified by a proof-of-concept converter prototype implemented in 0.374 mm2 of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support output voltages of 0.5 V-1.2 V from a 2 V input supply, and achieves 79.76% efficiency at an output power density of 0.86 W/mm2 .

Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters

THIS paper explores opportunities and challenges in power conversion in the VHF frequency range of 30-300 MHz. The scaling of magnetic component size with frequency is investigated, and it is shown that substantial miniaturization is possible with increased frequencies even considering material and heat transfer limitations. Likewise, dramatic frequency increases are possible with existing and emerging semiconductor devices, but necessitate circuit designs that either compensate for or utilize device parasitics. We outline the characteristics of topologies and control methods that can meet the requirements of VHF power conversion, and present supporting examples from power converters operating at frequencies of up to 110 MHz.

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Opportunities and Challenges in Very High Frequency Power Conversion

Power density of power electronic converters in different applications has roughly doubled every 10 years since 1970. Behind this trajectory was the continuous advancement of power semiconductor device technology allowing an increase of converter switching frequencies by a factor of 10 every decade. However, today's cooling concepts, and passive components and wire bond interconnection technologies could be major barriers for a continuation of this trend. For identifying and quantifying such technological barriers this paper investigates the volume of the cooling system and of the main passive components for the basic forms of power electronics energy conversion in dependency of the switching frequency and determines switching frequencies minimizing the total volume. The analysis is for 5 kW rated output power, high performance air cooling, advanced power semiconductors, and single systems in all cases. A power density limit of 28 kW/dm3@300 kHz is calculated for an isolated DC-DC converter considering only transformer, output inductor and heat sink volume. For single-phase AC-DC conversion a general limit of 35 kW/dm3 results from the DC link capacitor required for buffering the power fluctuating with twice the mains frequency. For a three-phase unity power factor PWM rectifier the limit is 45 kW/dm3@810 kHz just taking into account EMI filter and cooling system. For the sparse matrix converter the limiting components are the input EMI filter and the common mode output inductor; the power density limit is 71 kW/dm3@50 kHz when not considering the cooling system. The calculated power density limits highlight the major importance of broadening the scope of research in power electronics from traditional areas like converter topologies, and modulation and control concepts to cooling systems, high frequency electromagnetics, interconnection technology, multi-functional integration, packaging and multi-domain modeling and simulation to ensure further advancement of the field along the power density trajectory.

https://www.hpe.ee.ethz.ch/uploads/tx_ethpublications/IEEJ_PowerDensity_Paper_FinalRevised_03.pdf

PWM Converter Power Density Barriers

Intel's® 4th generation Core™ microprocessors are powered by Fully Integrated Voltage Regulators (FIVR). These 140 MHz multi-phase buck regulators are integrated into the 22nm processor die, and feature up to 80 MHz unity gain bandwidth, non-magnetic package trace inductors and on-die MIM capacitors. FIVRs are highly configurable, allowing them to power a wide range of products from 3W fanless tablets to 300W servers. FIVR helps enable 50% or more battery life improvements for mobile products and more than doubles the peak power available for burst workloads.

FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs

We present a 100MHz eight-phase synchronous buck converter using air-core inductors. The voltage regulator (VR) chip was manufactured in a 90nm CMOS process and mounted on a flip-chip test package together with surface-mount inductors and decoupling capacitors. The measured peak efficiency is 84.0% for Vin/Vout= 2.4V/1.5V and 79.3% for 2.4V/1.2V. The VR delivers a load current of 12A in an area of only 25mm2 and 2.5mm height. This is the first demonstration of a high-frequency VR with air-core inductors, that reaches a record power density of 3.78kW/in3.

A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors

Intel fourth-generation and fifth-generation Core microprocessors are powered by high-frequency integrated switching voltage regulators. The inductors required to implement these regulators are constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the construction of these inductors including representative results from production packages. Measured inductors reported in this paper span from 1 to 6.7 nH under 2.4 mm2 and achieve $Q$ of up to 24 at 140 MHz (the switching frequency).

Package Inductors for Intel Fully Integrated Voltage Regulators

Microelectronic packages continue to undergo significant changes to keep pace with the demands of high- performance silicon. From the traditional role of space transformation and mechanical protection, packages have evolved to be a means to cost-effectively manage the increasing demands of power delivery, signal distribution, and heat removal. In the last decade or so, increasing frequency and power levels coupled with lower product costs have been driving new package technologies. Some examples of this are the migration from wirebond to flip chip interconnect and ceramic to organic package substrates. Recently, architectural changes like the introduction of multicore processors, material changes such as the low-K dielectrics on the silicon, and lead-free second-level interconnects have introduced a new set of challenges that require innovative package technology solutions. As we look forward, increased levels of current, increased power density, and high-bandwidth signaling are expected to create challenges in all disciplines within the package field. In addition to these technical challenges, market forces such as declining computer prices, increased user experience through miniaturized devices, wireless connectivity, and longer battery life would make these challenges even more complex. In this paper we provide an overview of trends and challenges in the areas of power delivery, signal transfer, thermal management, miniaturization, and wireless package technologies. We also examine some of the potential solutions that are being developed to meet these challenges.

Advanced Package Technologies for High-Performance Systems

An embodiment of the present invention is a technique to integrate passive components in a die assembly. A capacitor, inductor, or resistor is integrated on a spacer between upper and lower dies in stacked dies. Conductors are attached to the capacitor, inductor or resistor to connect the capacitor, inductor, or resistor to at least one of the upper and lower dies.

Kaladhar Radhakrishnan

Papers

FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs

A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors

Package Inductors for Intel Fully Integrated Voltage Regulators

Advanced Package Technologies for High-Performance Systems

Integrating passive components on spacer in stacked dies