An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Frontiers of silicon-on-insulator

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

Multiple-gate SOI MOSFETs: device design guidelines

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

Three dimensional device integration method and integrated device

Buried SiO2, layers were formed by oxygen-ion (14O+) implantation into silicon. The impurity distribution of the oxygen-implanted silicon substrate was analysed by auger spectroscopy. The epitaxially-grown silicon layer on this substrate showed a good monocrystalline structure, and a 19-stage c.m.o.s. ring oscillator exhibited high performance in operation.

C.M.O.S. devices fabricated on buried SiO2 layers formed by oxygen implantation into silicon

The structure of SIMOX wafers implanted at 180 keV with doses of 0.1 × 1018-2.0 × 101816O+ cm−2 at 550 °C, followed by annealing over the temperature range of 1050–1350 °C, has been investigated using cross-sectional transmission electron microscopy and a chemical etching. With doses of 0.35 × 1018-0.4 × 1018 cm−2, a continuous buried oxide layer having no Si island inside is formed by high-temperature annealing at 1350 °C. At a dose of 0.7 × 1018 cm−2, multilayered oxide striations appear in the as-implanted wafer. These striations grow into multiple buried oxide layers after annealing at 1150 °C. The multiple layers lead to a discontinuous buried oxide layer, resulting in the formation of a number of Si micropaths between the top Si layer and the Si substrate when the wafer is annealed at 1350 °C. These Si paths cause the breakdown electric field strength of the buried oxide layer to deteriorate. With doses of 0.2 × 1018-0.3 × 1018 cm−2 and of higher than 1.3 × 1018 cm−2, an extremely high density of threading dislocations is generated in the top Si layer after annealing at 1350 °C. The dislocation density is greatly reduced to less than 103 cm−2 when the oxygen dose falls in the range of 0.35 × 1018-1.2 × 1018 cm−2. Here we propose a mechanism that accounts for the threading dislocation generation at substoichiometric oxygen doses of less than 1.2 × 1018 cm−2.

Analysis of buried oxide layer formation and mechanism of threading dislocation generation in the substoichiometric oxygen dose region

A 0.1- mu m-gate CMOS/SIMOX (separation by implanted oxygen) has been successfully fabricated using high quality SIMOX substrates and an advanced design concept for the subquarter-micron region based on a simple device model. In addition, both 85-nm-gate n- and p-MOSFETs/SIMOX with 8-nm-thick silicon active layer have been realized. High parasitic resistance in the source and drain regions of the 0.1- mu m-gate CMOS/SIMOX tends to increase the propagation delay time. However, 0.1- mu m-gate CMOS/SIMOX devices with a delay time as low as 10 ps can be obtained by reducing the parasitic resistance. >

0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer

A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.

SOI substrate and method of producing the same

The structure of separation by implanted oxygen (SIMOX) wafers oxidized at temperatures from 1000 to 1350°C has been investigated using cross-sectional transmission electron microscopy and spectroscopic ellipsometry. By high-temperature oxidation at 1350°C, a 43 nm thick internal thermal oxide (ITOX) layer is grown between the top Si layer and the buried oxide layer formed by oxygen implantation and subsequent annealing. The resulting buried-oxide thickness is one and one-half times the original. The thickness of ITOX increases with increasing oxidation temperature. In addition, the superficial thermal oxide layer formed on the SIMOX wafers during the oxidation is somewhat thinner than that on the bulk Si wafers. A mechanism to account for both superficial thermal oxidation and internal thermal oxidation is proposed. The top Si-buried oxide interface, where some oxygen atoms react with Si during high-temperature oxidation, acts as a sink for them and causes them to diffuse more easily through the thin top Si layer to the interface.

Katsutoshi Izumi

Papers

C.M.O.S. devices fabricated on buried SiO2 layers formed by oxygen implantation into silicon

Analysis of buried oxide layer formation and mechanism of threading dislocation generation in the substoichiometric oxygen dose region

0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer

SOI substrate and method of producing the same

Investigations on High‐Temperature Thermal Oxidation Process at Top and Bottom Interfaces of Top Silicon of SIMOX Wafers