Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

Drain current versus drain voltage characteristics for an analytical Al0.25Ga0.75N/GaN superlattice MOSFET

Analysis of electron transport in AlGaN/GaN superlattice HEMTs for isotopes 14 N and 15 N

Modelling of InAs nanowire and MOSFET under phonon emission and absorption by using NEGF formalism

Modern comparative approach for carrier transport in InAlN/AlN superlattice device with characteristics and modelling using nitride (14N,15N) isotopes

Study of the carrier transport in presence of backscattering in InAs nanowire based MOSFET after GaN

In this paper authors have studied the variation of mobility with device length due to total scattering and ballistic transport in AlGaN/GaN superlattice structure. Here comparisons have also been made between mobility due to total scattering and ballistic transport. Subsequently comparative analysis of power dissipation has also been studied here.

Mobility and power dissipation due to total phonon scatterings compared with ballistic transport in AlGaN/GaN superlattice

In this research work a 10 bit SAR(Successive Approximation Register) type ADC(Analog to Digital Converter) IP(Intellectual Property) has been approached with some specifications along with the circuit diagram of each elementary design block. Here 180 nm technology has been used. Various types of performance parameters like area, resolution, i/p current, i/p impedance, conversion time etc. have been discussed. Also the pre-layout as well as post layout simulation results have been given in this paper.

Kaushik Mazumdar

Papers

Study of the carrier transport in presence of backscattering in InAs nanowire based MOSFET after GaN

Drain current versus drain voltage characteristics for an analytical Al0.25Ga0.75N/GaN superlattice MOSFET

Modelling of InAs nanowire and MOSFET under phonon emission and absorption by using NEGF formalism

Mobility and power dissipation due to total phonon scatterings compared with ballistic transport in AlGaN/GaN superlattice

Power Optimized 10 Bit ADC IP Design in Transistor Level