An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

Logic circuit utilizing pass transistors and logic gate

A logical processing part is formed by a pass transistor logic element, and an output signal of the pass transistor logic element is applied to the gates of MOS transistors for differentially amplifying and latching the output signal in the latch stage. This latch stage is formed by master and slave latch circuits, and power supply to the master latch circuit is cut off while holding an information signal only in the slave latch circuit with the level of a power supply voltage thereto increased, reducing a leakage current in a sleep mode or a power down mode. A logic circuit correctly operating at a high speed with low current consumption under a low power supply voltage is provided.

Semiconductor logic circuit device of low current consumption

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

A high-speed dynamic logic circuit having a high tolerance to noise includes pMOS and nMOS transistors constructing a buffer, which is connected to an internal dynamic node, for driving an output terminal. Only the pMOS transistor, which operates in an evaluation cycle, is connected to the dynamic node. The nMOS transistor is driven by a signal that is the inverse of a precharge signal. A weak latch, or an nMOS transistor of minimum size driven by the dynamic node, is connected to the output terminal as a leakage compensation circuit.

Dynamic logic circuit

The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them

PURPOSE:To obtain a semiconductor integrated circuit operating with a low power consumption by constituting a data output part and a data input part to be connected with data lines by a single FET and preventing a through current from flowing while making the load capacitance of data lines small. CONSTITUTION:When control signals 113, 114 of a buss TR logic 110 are respective an H and an L, the n type FET 122 of an integrated circuit 120 is turned OFF and the single (p) type FET 124 of the data input part and the data output part is turned ON and a (p) type FET 125 is turned OFF and then an output becomes the H. At this time, FETs 122, 125 are completely turned OFF to make the load capacitance of data lines small and the through current of a DC. current is not allowed to flow through a circuit 120. At the time the signal 114 is the H, the single (n) type FET 122 becoming the data input part and the data output part is turned ON to make the output the L in a like manner and also FETs 123, 124 are turned OFF and then the same result is obtained. Semiconductor integrated circuits such as small-sized semiconductor storage circuit and so forth operating at high speed with a low power consumption are obtained by making an input signal a low amplitude with a constitution having the small number of TRs.

Gate circuit, semiconductor integrated circuit, semiconductor storage circuit and semiconductor integrated circuit device using them, information processing device using them

Kayoko Nemoto

Papers

Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them

Gate circuit, semiconductor integrated circuit, semiconductor storage circuit and semiconductor integrated circuit device using them, information processing device using them