An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The goal of this paper is to review in brief the basic physics of single-election devices, as well as their-current and prospective applications. These devices based on the controllable transfer of single electrons between small conducting "islands", have already enabled several important scientific experiments. Several other applications of analog single-election devices in unique scientific instrumentation and metrology seem quite feasible. On the other hand, the prospect of silicon transistors being replaced by single-electron devices in integrated digital circuits faces tough challenges and remains uncertain. Nevertheless, even if this replacement does not happen, single electronics will continue to play an important role by shedding light on the fundamental size limitations of new electronic devices. Moreover, recent research in this field has generated some by-product ideas which may revolutionize random-access-memory and digital-data-storage technologies.

Single-electron devices and their applications

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

III. Formation of Carbon Clusters 2317 IV. Thermodynamic Properties 2319 V. C2 2319 A. Structure and Spectroscopy 2319 B. C2 2320 C. C2 2321 VI. C3 2321 A. Early Experimental Work 2321 B. Mid-IR and Far-IR Spectroscopy 2321 C. Electronic Spectroscopy 2323 1. The Σu + Ground State 2323 2. The AΠu State 2324 3. The Σu + State 2324 4. The aΠu and bΠg States 2325 5. Other Band Systems 2326 D. C3 in the Interstellar Medium 2326 E. C3 2326 F. C3 2327 VII. C4 2327 A. Theory 2327 B. Experiment 2328 1. The Rhombic Isomer 2328 2. The Linear Isomer 2328 C. Excited Electronic States 2330 D. C4 2331 E. C4 2332 VIII. C5 2332 A. Theory 2332 B. Experiment 2332 C. Excited Electronic States 2334 D. C5 2334 E. C5 2335 IX. C6 2335 A. Theory 2335 B. Experiment 2336 1. The Cyclic Isomer 2336 2. The Linear Isomer 2336 C. Excited Electronic States 2337 D. C6 2338 E. C6 2338 X. C7 2338 A. Theory 2338 B. Experiment 2338 C. Excited Electronic States 2340 D. C7 2340 E. C7 2340 XI. C8 2341 A. Theory 2341 B. Experiment 2342 1. The Cyclic Isomer 2342 2. The Linear Isomer 2342 C. Excited Electronic States 2342 D. C8 2342 E. C8 2342 XII. C9 2343 A. Theory 2343 B. Experiment 2343 C. Excited Electronic States 2345 D. C9 2345 E. C9 2345 XIII. C1

http://www.cchem.berkeley.edu/rjsgrp/publications/papers/1998/200_orden_1998.pdf

Small carbon clusters: spectroscopy, structure, and energetics.

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Improvement of threshold voltage deviation in damascene metal gate transistors

A MOSFET in which the gate electrode is formed of a polycrystalline silicon film, a silicon nitride film having a nitrogen surface density of lens than 8×10 14 cm -2 , and a tungsten film--these films formed one upon another in the order mentioned. The gate electrode thus formed, serves to shorten the delay time of the MOSFET.

Semiconductor device wiring or electrode

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

We propose a plasma and thermal damage-free gate process named the "Damascene gate process" where CMP (Chemical Mechanical Polishing) is used in forming the gate structure. By using this process, fully planarized high performance metal (W/TiN or Al/TiN) gate transistors with pure SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were fabricated with very uniform and highly reliable electrical characteristics. Therefore, this technology is useful in fabricating 0.1 /spl mu/m MOSFETs and beyond.

High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime

According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.

Kazuaki Nakajima

Papers

Improvement of threshold voltage deviation in damascene metal gate transistors

Semiconductor device wiring or electrode

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime

Semiconductor device and manufacturing method therefor