K
K. Suguro
Researcher at Toshiba
Publications - 53
Citations - 1492
K. Suguro is an academic researcher from Toshiba. The author has contributed to research in topics: MOSFET & Metal gate. The author has an hindex of 19, co-authored 53 publications receiving 1464 citations.
Papers
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Journal ArticleDOI
Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI
Toyota Morimoto,Tatsuya Ohguro,S. Momose,Toshihiko Iinuma,Iwao Kunishima,K. Suguro,I. Katakabe,Hiroomi Nakajima,Masakatsu Tsuchiaki,Mizuki Ono,Yasuhiro Katsumata,Hiroshi Iwai +11 more
TL;DR: In this article, a nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed, and it has been confirmed that a nickel film sputtered onto n/sup ± and p/sup +/- single-silicon and polysilicon substrates is uniformly converted into NiSi, without agglomeration, by lowtemperature (400-600/spl deg/C) rapid thermal annealing.
Proceedings ArticleDOI
Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length
K. Okano,Takashi Izumida,H. Kawasaki,Akio Kaneko,Atsushi Yagishita,Takahisa Kanemura,Masaki Kondo,Sanae Ito,Nobutoshi Aoki,Kiyotaka Miyano,T. Ono,K. Yahashi,K. Iwade,T. Kubota,T. Matsushita,Ichiro Mizushima,Satoshi Inaba,Kazunari Ishimaru,K. Suguro,Kazuhiro Eguchi,Y. Tsunashima,Hidemi Ishiuchi +21 more
TL;DR: In this article, a CMOS FinFET fabricated on bulk Si substrate is discussed from the viewpoint of device size scalability and short channel effect control, and a trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime.
Proceedings ArticleDOI
High-Performance FinFET with Dopant-Segregated Schottky Source/Drain
Akio Kaneko,Atsushi Yagishita,K. Yahashi,T. Kubota,M. Omura,K. Matsuo,Ichiro Mizushima,K. Okano,H. Kawasaki,Takashi Izumida,Takahisa Kanemura,Nobutoshi Aoki,A. Kinoshita,Junji Koga,Satoshi Inaba,Kazunari Ishimaru,Yoshiaki Toyoshima,Hidemi Ishiuchi,K. Suguro,Kazuhiro Eguchi,Y. Tsunashima +20 more
TL;DR: In this article, a DS-Schottky S/D CMOS-FinFET with dopant-segregated Schottky source/drain was demonstrated.
Proceedings ArticleDOI
A NiSi salicide technology for advanced logic devices
Toyota Morimoto,Hisayo Momose,Toshihiko Iinuma,Iwao Kunishima,K. Suguro,H. Okana,I. Katakabe,Hiroomi Nakajima,Masakatsu Tsuchiaki,Mizuki Ono,Yasuhiro Katsumata,Hiroshi Iwai +11 more
TL;DR: In this article, a nickel-silicide (NiSi) technology for deep submicron devices has been developed, and it was confirmed that Ni films sputtered on n- and p-single and polysilicon can be changed to mono-silicides (Ni Si) stably at low temperature (600 degrees C) over a short period without any agglomeration.
Journal ArticleDOI
Improvement of threshold voltage deviation in damascene metal gate transistors
Atsushi Yagishita,Tomohiro Saito,Kazuaki Nakajima,Seiji Inumiya,K. Matsuo,Tsuyoshi Shibata,Y. Tsunashima,K. Suguro,Tsunetoshi Arikado +8 more
TL;DR: In this paper, the work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors.