K
Kazuyasu Fujishima
Researcher at Mitsubishi
Publications - 67
Citations - 1662
Kazuyasu Fujishima is an academic researcher from Mitsubishi. The author has contributed to research in topics: Semiconductor memory & Dram. The author has an hindex of 25, co-authored 67 publications receiving 1660 citations.
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Patent
Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout
TL;DR: In this paper, the authors proposed an arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines, where dummy cells are provided at respective twisted portions of the dummy word line and the bit line.
Patent
Semiconductor memory device for simple cache system
TL;DR: In this article, the DRAM memory cell array is divided into a plurality of blocks each comprising of columns corresponding to the blocks in the SRAM memory array, and data corresponding to one row in each of the blocks is transferred to another row in the corresponding block in the array.
Journal ArticleDOI
Twisted bit-line architectures for multi-megabit DRAMs
TL;DR: Twisted bit-line architectures to reduce or eliminate the noise are proposed and demonstrated by the soft-error rate improvement of a 1-Mb DRAM, and they are shown to be promising candidates for overcoming the scaling problems of DRAMs.
Patent
Cache contained type semiconductor memory device and operating method therefor
TL;DR: In this article, a dynamic random access memory with a fast serial access mode for use in a simple cache system includes a plurality of memory cell blocks prepared by division of a memory cell array.
Patent
Semiconductor memory device containing a cache and an operation method thereof
TL;DR: In this paper, a DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory array.