Showing papers in "IEEE Journal of Solid-state Circuits in 1989"

Matching properties of MOS transistors

Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >

High-speed CMOS circuit technique

Abstract: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

A noise-shaping coder topology for 15+ bit converters

Abstract: A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3- mu m CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate. >

ISAAC: a symbolic simulator for analog integrated circuits

Abstract: The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The program's capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm. >

An architecture for electrically configurable gate arrays

Abstract: An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible, and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead needed to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. This circuitry can also be used to test the device prior to programming and observe internal nodes after programming. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated. >

ILAC: an automated layout tool for analog CMOS circuits

Abstract: ILAC (interactive layout of analog CMOS circuits) is a process-independent tool that automatically generates geometrical layout for analog CMOS cells from a circuit description. ILAC handles typical analog layout constraints such as device matching, symmetry, and distance and coupling constraints. ILAC supports user-specified constraints on cell height and input/output pin locations. Together with the design tool IDAC (interactive design for analog circuits), ILAC makes a fully functional analog CMOS cell compiler that automatically produces geometrical layout from functional specifications for a library of circuits including amplifiers, voltage and current references, comparators, oscillators, and A/D (analog-to-digital) converters. >

Operational transconductance amplifier-based nonlinear function syntheses

Abstract: It is shown that the operational transconductance amplifier, as the active element in basic building blocks, can be efficiently used for programmable nonlinear continuous-time function synthesis. Two efficient nonlinear function synthesis approaches are presented. The first approach is a rational approximation, and the second is a piecewise-linear approach. Test circuits have been fabricated using a 3- mu m p-well CMOS process. The flexibility of the designed and tested circuits was confirmed. >

Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits

Abstract: Most of the presently available EEPROM circuits feature 5-V-only operation and therefore incorporate on-chip high-voltage generators. In spite of the importance of these latter circuits, a thorough analysis of the circuit has not been presented. In this paper the characteristics of the voltage multiplier circuit are thoroughly analyzed and modeled. The results obtained from this analysis are fully confirmed by experiments. The degradation characteristics of the circuit are discussed and its capability to compensate for nonvolatile memory degradation is shown. >

A ternary content addressable search engine

Abstract: The design, implementation, and experimental results for a ternary content addressable search engine chip, known as the Database Accelerator (DBA), are discussed. The DBA chip architecture is presented. It is well suited to serve as a coprocessor for a variety of logic search applications. The core of the DBA system is composed of novel high-density content addressable memory (CAM) cells capable of storing three states. The design of these cells and their support circuitry are described. The CAM cell and support circuitry were fabricated and their operation confirmed. The circuit implementation of the DMA data path is described with particular emphasis on the optimization of the multiple response resolver. The timing and control methodology, which simultaneously satisfies the complexity, speed, and robustness requirements of the DBA chip, are reported. Experimental DBA chip results that verify the full functionality and testability of the design are presented. >

A very-high-slew-rate CMOS operational amplifier

Abstract: The amplifier uses a circuit to inject an extra bias current into a conventional source-coupled CMOS differential input stage in the presence of large differential input signals. This measure substantially increases the slew rate of an operational amplifier for a given quiescent current. The performance of the amplifier is compared to a conventional operational amplifier when used in a sample-and-hold circuit. The maximum operating clock frequency of the sample-and-hold increases from 290 kHz to 1 MHz with a hold capacitor of 1 nF. The amplifier has been fabricated in a 5- mu m CMOS process and dissipates a static power of 7.5 mW. >

Metastability behavior of CMOS ASIC flip-flops in theory and test

Abstract: Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules. >

A 10-bit 5-Msample/s CMOS two-step flash ADC

Abstract: A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

SPIM: a pipelined 64*64-bit iterative multiplier

Abstract: A 64*64-bit iterating multiplier, the Stanford pipelined iterative multiplier (SPIM), is presented. The pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a partial array to be used, which reduces area. SPIM was fabricated in a 1.6- mu m CMOS process. It has a core size of 3.8 mm*6.5 mm and contains 41000 transistors. The on-chip clock generator runs at an internal clock frequency of 85 MHz. The latency for a 64*64-bit fractional multiply is under 120 ns, with a pipeline rate of one multiply every 47 ns. >

A CMOS electrically configurable gate array

Abstract: A CMOS electrically configurable gate array that combines the flexibility, efficiency, extendability, and performance of mask-programmed gate arrays with the convenience of user programmability is described. The implementation is facilitated by a novel two-terminal antifuse programmable element and a configurable interconnect technology. The chip has been fabricated using 2- mu m n-well CMOS technology with two-layer metallization. >

Design procedures for a fully differential folded-cascode CMOS operational amplifier

Abstract: A fully differential folded-cascode op. amp. is analyzed, and the results are presented in the form of design equations and procedures. Tradeoffs among such factors as bandwidth, gain, phase margin, bias currents, signal swing, slew rate, and power are made evident. Closed-form expressions are developed, and a sequence of design steps is established. A graphical representation of the relationships among the gain, power, and phase margin for different capacitive loadings is presented to illustrate visually one form of design optimization. The results of SPICE simulations are shown to agree very well with the design equations presented. >

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluation

Abstract: The development is described of a sigma-delta A/D (analog-to-digital) converter Included is a brief overview of sigma-delta conversion The A/D converter achieves an 885-dB dynamic range and a maximum signal-to-noise ratio of 815 dB The harmonic distortion is negligible This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 1024 MHz Transconductance amplifiers having a 160-MHz f/sub t/ were developed for the integrators The circuit is implemented in a 175- mu m 5-V CMOS process The analog circuitry occupies 2 mm/sup 2/ of silicon area and consumes 75 mW of power Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described The design of a sigma-delta development and performance evaluation system is presented This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software >

Dummy transistor compensation of analog MOS switches

Abstract: Theoretical and experimental results of the clock-feedthrough phenomenon (charge injection) in sample-and-hold circuits using minimum features size transistors of a self-aligned 3 mu m CMOS technology are compared. The lumped RC model of the conductive channel is used and verified in different switch configurations with variable input voltages. Special emphasis is placed on the feasibility and limits of charge cancellation techniques using dummy switches. >

An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application

Abstract: A multiple-level 2-bit/cell storage technique for DRAMs (dynamic random-access memories) has been developed. The total RAM area is reduced and the cell array is cut in half. Since the memory cell area is especially defect-sensitive, this technique is highly effective for process yield improvement. Reasonable access time has been realized with this technique: 170 ns is still fast enough for many ASIC (application-specific integrated circuit) memory applications. This technique meets the requirement of high density and moderate speed. It was found that the 2-bit/cell storage technique is suitable for macrocell or memory-on-logic type application. >

A set of four ICs in CMOS technology for a programmable hearing aid

Abstract: A four-chip system developed for a programmable hearing aid is presented. It combines E/sup 2/PROM (electrically erasable programmable read-only memory) memories with a control logic, low-noise preamplifiers, AGC (automatic gain control) amplifiers, SC (switched-capacitor) filters, voltage multipliers, and an output amplifier of the pulse-width type. The implementation of the critical parts is explained. The 3- mu m self-aligned-contacts MOS technology of the Faselec company is used. The system is supplied by a single 1.3-V battery and its typical current consumption is 1.5 mA. The whole system can be connected to a computer. >

A 20 kbit associative memory LSI for artificial intelligence machines

Abstract: A 20 kb (512 words*40 b) CMOS associative-memory LSI is described. This LSI performs large-scale parallelism for highly efficient associative operations in artificial intelligence machines. Relational search, large-bit-length data treatment, and quick garbage collection are realized on the single-chip associative-memory LSI. A cell array structure has been designed in order to reduce the chip area. A newly designed simple accelerator circuit allows for high-speed search operations. The LSI is fabricated using 1.2 mu m double-aluminium-layer CMOS process technology. 284000 devices have been integrated on a 5.3*7.9 mm/sup 2/ chip. The measured minimum cycle time and power dissipation at 10 MHz operation are 85 ns and 250 mW, respectively. The associative memory, with its highly efficient associative operation capabilities, promises to be a large step toward the development of high-performance artificial intelligence machines. >

A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS

Abstract: A variable-gain amplifier (VGA) with a gain range of 50 dB has been implemented in a standard 3 mu m CMOS process using parasitic lateral and vertical bipolar transistors to form the core of the circuit. The bipolar transistors had been characterized extensively. The VGA has a bandwidth larger than 3 MHz over the whole gain range and operates on a single 5 V power supply. The active area is about 0.8*0.9 mm/sup 2/. >

Ultrafast compact 32-bit CMOS adders in multiple-output domino logic

Abstract: A dynamic CMOS logic style, called multioutput domino logic (MODL), has been developed. In this logic style, single logic gates produce multiple functions, and a circuit's device count can be reduced by a factor of more than 2, depending on the degree of recurrence in the circuit. In addition, MODL circuits are, by construction, considerably more stable than other dynamic circuits including conventional domino. A 32-bit carry lookahead (CLA) structure which reduces the adder's worst-case path by two logic stages has also been devised. This CLA structure has been developed to effectively utilize the advantages of MODL. Taken together, these developments have resulted in two 32-bit CMOS adders, providing area and speed improvements of 1.5* and 1.7* over the combination of the domino and conventional CLA techniques. Both adders have been fabricated in a standard 0.9- mu m two-level metal CMOS technology, and measured results show that the straight adder has achieved 32-bit addition times of less than 3.1 ns at 25 degrees C with V/sub DD/+5.0 V. >

Twisted bit-line architectures for multi-megabit DRAMs

Abstract: As the memory cell array of DRAM has been scaled down, inter-bit-line coupling noise has emerged as a serious problem. The signal loss due to this noise is estimated at about 40% of the signal amplitude in a polycide-bit-line 16-Mb DRAM with a technologically attainable scaling scheme. Twisted bit-line architectures to reduce or eliminate the noise are proposed and demonstrated by the soft-error rate improvement of a 1-Mb DRAM. The effective critical charge is improved by 35%, which is attributed not only to the improvement of the signal amplitude but also to the elimination of large coupling noise during the sensing operation. The impact of these twisted bit-line architectures from a scaling viewpoint is also examined, and they are shown to be promising candidates for overcoming the scaling problems of DRAMs. >

Influence of device parameters on the switching speed of BiCMOS buffers

Abstract: The influence of different MOS and bipolar device parameters on the switching speed of a BiCMOS buffer is described. This influence is studied by looking at the response of a BiCMOS inverter to a step input. Using suitable approximations for the high-level injection effects in the bipolar transistor, mathematical approximations for the response are derived. The approximate responses are compared to those determined by SPICE simulations and the agreement is satisfactory. High-current effects in the bipolar transistor strongly affect the performance. The effects of different bipolar transistor parasitic resistors are investigated, and it is found that only the collector resistance is important. The influence of different emitter sizes on the delay time is studied, and it is shown that for a given area, there is one optimal size ratio for the MOS and bipolar transistors for which the delay is minimum. >

A programmable analog neural network chip

Abstract: A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10/sup 3/ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00*3.5-mm/sup 2/ die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2*10/sup 9/ weight changes/second and exceeding the throughput of 'neural network accelerators' by two orders of magnitude. >

Towards an analog system design environment

Abstract: An analog circuit design environment and its key features are presented These are multifunctionality, advanced modeling, novel simulation approaches, general sizing algorithms, hierarchy, and automatic and interactive layout generation capabilities Also, several developments in the field of analog design automation are discussed >

A fully differential sample-and-hold circuit for high-speed applications

Abstract: A new design technique for realizing a true fully differential sample-and-hold (S/H) circuit is presented. This technique avoids the reset phase and consequently the need for a high slew rate for the operational amplifier, it therefore can be used for high-speed applications. A prototype circuit, which occupies 0.1 mm/sup 2/ in a 3- mu m CMOS process, is integrated and experimental results are presented. >

A 90-ns one-million erase/program cycle 1-Mbit flash memory

Abstract: Describes the design and performance of a 245-mil/sup 2/ 1-Mbit (128K*8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.0- mu m EPROM-base technology, the 15.2- mu m/sup 2/ single-transistor EPROM tunnel oxide (ETOX) cell requires only 42 percent of the area required by the previous 1.5- mu m device. One of the most significant aspects of this 1-Mbit flash memory is the one-million erase/program cycle capability. The 1-Mbit memory exhibits 90-ns read access time while the reprogramming performance gives a 900-ms array erase time and a 10- mu s/byte programming rate. Ample erase and program margins through one-million erase/program cycles are guaranteed by the internal verify circuits. Column redundancy is implemented with the utilization of flash memory cells to store repaired addresses. >

A built-in Hamming code ECC circuit for DRAMs

Abstract: An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique. >

Design of a neural-based A/D converter using modified Hopfield network

Abstract: The architecture associated with the Hopfield network can be utilized in the VLSI realization of several important engineering optimization functions for signal processing purposes. The properties of local minima in the energy function of Hopfield networks are investigated. A design technique to eliminate these local minima in the Hopfield neural-based analog-to-digital converter has been developed. Experimental data agree well with theoretical results in the output characteristics of the neural-based data converter. >