There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.

Networks on chips: a new SoC paradigm

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

/pdf/a-survey-of-research-and-practices-of-network-on-chip-2rc0mlsrfq.pdf

A survey of research and practices of Network-on-chip

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

/pdf/modeling-the-effect-of-technology-trends-on-the-soft-error-7cmde8sa08.pdf

Modeling the effect of technology trends on the soft error rate of combinational logic

The CoRAM memory architecture for FPGA-based computing augments traditional reconfigurable fabric with a natural and effective way for applications to interact with off-chip memory and I/O. The two central tenets of the CoRAM memory architecture are (1) the deliberate separation of concerns between computation versus data marshalling and (2) the use of a multithreaded software abstraction to replace FSM-based memory control logic. To evaluate the viability of the CoRAM memory architecture, we developed a full RTL implementation of a CoRAM microarchitecture instance that can be synthesized for standard cells or emulated on FPGAs. The results of our evaluation show that a soft emulation of the CoRAM memory architecture on current FPGAs can be impractical for memory-intensive, large-scale applications due to the high performance and area penalties incurred by the soft mechanisms. The results further show that in an envisioned FPGA built with CoRAM in mind, the introduction of hard macro blocks for data distribution can mitigate these inefficiencies---allowing applications to take advantage of the CoRAM memory architecture for ease of programmability and portability while still enjoying performance and efficiency comparable to RTL-level application development on conventional FPGAs.

/pdf/prototype-and-evaluation-of-the-coram-memory-architecture-5ak8yq107u.pdf

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing

The crossbar is a popular topology for on-chip networks that offers non-blocking connectivity and uniform latency. However, as the number of nodes increases, crossbars typically scale poorly in area, power, and latency/throughput. To better understand the design space, we have developed an on-chip crossbar modeling tool based on analytical models calibrated using circuit-level simulation results in 40nm CMOS. We present a design space exploration showing how crossbar area, power, and performance vary across input/output node number, data width, wire parameters, and circuit implementation. Using the modeling results, we identify a design point that demonstrates 2X higher throughput, 1.4X lower power and 1.2X lower area compared to previous published designs.

Modeling and Design of High-Radix On-Chip Crossbar Switches

Differential power analysis (DPA) has been shown to be an effective attack on cryptographic systems capable of revealing secret data by measuring power consumption. DPA-resistant circuits currently incur severe penalties in terms of performance, area, and power - as much as 4times in each. Additionally, most are dual-rail logic families, which can require careful attention to wire routing to ensure balanced output loads. We present three-phase single-rail precharge logic (TSPL), a single-rail dynamic logic family with high DPA resistance and significantly lower overheads in performance, area, and power than other DPA-resistant logic styles.

Extended abstract: A high-performance, low-overhead, power-analysis-resistant, single-rail logic style

Differential power analysis (DPA) has been shown to be a highly effective and easy to mount side-channel attack. One effective method of increasing DPA resistance is to use three-phase dual-rail pre-charge logic (TDPL), but this type of logic is vulnerable to manipulation of the clock generation/distribution hardware. If an attacker can slow down the clock, separate the evaluate phase from the discharge phase, or eliminate the discharge phase entirely, the DPA resistance of TDPL is no better than a basic dynamic dual rail logic family. To counter such attacks, we propose a self-timed three-phase dual-rail pre-charge logic family (ST-TDPL), which internally generates the discharge clock in a distributed manner. Thus, an attacker cannot split the discharge phase from the evaluate phase. We compare the area, energy, and normalized energy deviation (NED) of ST-TDPL against Simple TDPL, Simple TDPL with no discharge phase, and static CMOS using an iso-performance design point (i.e., all gates have the same delay) in an industrial 65nm bulk CMOS. The results show that ST-TDPL achieves a similarly low NED value as TDPL, while also providing protection against attacks on the clocking infrastructure.

A DPA-resistant self-timed three-phase dual-rail pre-charge logic family

SRAM design in scaled technologies requires knowledge of phenomena at the process, circuit, and architecture level. Decisions made at various levels of the design hierarchy affect the global figures of merit (FoMs) of an SRAM, such as, performance, power, area, and yield. However, the lack of a quick mechanism to understand the impact of changes at various levels of the hierarchy on global FoMs makes an accurate assessment of SRAM design innovations difficult. Thus, we introduce Virtual Prototyper (ViPro), a tool that helps SRAM designers explore the large design space by rapidly generating optimized virtual prototypes of complete SRAM macros. It does so by allowing designers to describe the SRAM components with varying levels of detail and by incorporating them into a hierarchical model that captures circuit and architectural features of the SRAM to optimize a complete prototype. It generates base-case prototypes that provide starting points for design space exploration, and assesses the impact of process, circuit, and architectural changes on the overall SRAM macro design.

Ken Mai

Papers

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing

Modeling and Design of High-Radix On-Chip Crossbar Switches

Extended abstract: A high-performance, low-overhead, power-analysis-resistant, single-rail logic style

A DPA-resistant self-timed three-phase dual-rail pre-charge logic family

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers