There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.

Networks on chips: a new SoC paradigm

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

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A survey of research and practices of Network-on-chip

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

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Modeling the effect of technology trends on the soft error rate of combinational logic

Design methodologies for synthesizing FPGA fabrics presented in the literature typically employ a bottom-up approach wherein individual tiles are synthesized in isolation and later stitched together to generate the large FPGA fabric. However, using a bottom-up methodology to ensure fabric-level performance targets is challenging due to the lack of a global timing view across multiple tiles spanning the FPGA fabric. While previous works address this problem with a combination of manual buffering and floorplanning, these additional steps introduce significant deviations from standard push-button ASIC flows. In this paper, a top-down synthesis methodology is proposed, which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric. To evaluate the proposed design methodology, we developed an FPGA fabric generator using the Chisel hardware construction language. The fabric generator reads in the Verilog-to-Routing architecture file, describing the user-defined FPGA fabric, and generates the Verilog netlist and timing exceptions required to automatically place and route the FPGA fabric in any technology node with a standard cell library. Post layout timing analysis of placed and routed FPGA fabrics on a 28nm industrial CMOS process demonstrates that the top-down methodology can place and route fabrics without the need for any manual buffering or floorplanning while providing ~20% average improvement in performance across multiple benchmark designs.

A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow

A designer's intent and knowledge about the critical issues and trade-offs underlying a custom circuit design are implicit in the simulations she sets up for design creation and verification. However, this knowledge is tightly conjoined with technology-specific features and decoupled from the final schematic in traditional design flows. As a result, this knowledge is easily lost when the technology specifics change. This paper presents a Technology Agnostic Simulation Environment (TASE), which is a tool that uses simulation templates to capture the designer's knowledge and separate it from the technology-specific components of a simulation. TASE also allows the designer to form groups of related simulations and port them as a unit to a new technology. This allows an actual design schematic to remain tied to the analyses that illuminate the underlying trade-offs and design issues, unlike the case where schematics are ported alone. Giving the designer immediate access to the trade-offs, which are likely to change in new technologies, accelerates the re-design that often must accompany porting of complicated custom circuits. We demonstrate the usefulness of TASE by investigating Read and Write noise margins for a 6T SRAM in predictive technologies down to 16 nm.

/pdf/a-technology-agnostic-simulation-environment-tase-for-243k5b7vub.pdf

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

Protecting hardware IP from reverse engineering threats is becoming increasingly challenging with advances in reverse engineering techniques. Different camouflaged logic families based on multi-Vt transistors have been recently proposed to combat reverse engineering threats. While multi-Vt based camouflaged logic gates offer cells that have an identical layout with multiple functionalities, they typically incur significant overheads in power, area, and delay. Moreover, amplifying the threshold voltage difference to logic levels while maintaining the noise margins needs careful analysis of PVT variations and mismatch. In this paper, a Pseudo-Static Camouflaged (PS-CAMO) logic family is proposed to improve the energy overheads of camouflaged logic gates while maintaining the reliability and yields of static CMOS logic gates. Post-layout simulations of a high-performance fully camouflaged S-box in a 65nm industrial CMOS process shows a 42% reduction in energy and a 26% reduction in area compared to a previously proposed Threshold Voltage Defined (TVD) camouflaged logic family.

A compact energy-efficient pseudo-static camouflaged logic family

The emergence of multi-core architectures—driven by continued technology scaling—has led to concerns about increasing soft- and hard-error rates in commodity designs. Because modern chip designs consist of multiple high-speed clock domains, conventional lockstepped redundant execution is no longer practical. Recent work suggests an asynchronous approach to redundant execution, where processor pairs independently execute an instruction stream and treat any differences like soft errors, invoking rollback recovery. Because prior designs buffer instruction results within the out-of-order instruction window, they are limited to tightly coupled redundancy within a single chip, which limits availability and serviceability in the presence of hard errors. We propose REDAC, a set of lightweight mechanisms for distributed, asynchronous redundancy within a sharedmemory multiprocessor. REDAC provides scalable buffering for unchecked state updates, permitting the distribution of redundant execution across multiple nodes of a scalable shared-memory server. The REDAC mechanisms achieve high performance by enabling speculation across common serializing instructions and mitigating the effects of input incoherence. We evaluate REDAC using cycle-accurate fullsystem simulation of common enterprise workloads and show that performance overheads average just 10% when compared to a non-redundant system. These results are comparable to the performance of a similarly configured lockstep design, but offer the substantial benefits of asynchronous redundancy.

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REDAC: Distributed, Asynchronous Redundancy in Shared Memory Servers

Side channel attacks exploit inadvertent information leakage from the physical implementation of computing systems, bypassing the theoretical strength of cryptographic algorithms. Of particular concern are software side-channel attacks which can be mounted remotely without access or alteration of the hardware system. One type of attack that has been demonstrated to be highly effective is cache timing attacks that exploit cache replacement policies to discern information about the data being processed. In this paper, we present a secure cache design that defeats software side-channel attacks targeted at hardware caches. The memory-to-cache mapping is dynamic and randomized by replacing the address decoder of a conventional cache with a CAM. We fabricated a prototype 32kB secure cache along with a conventional 8-way version for comparison on a 65nm bulk CMOS process. The prototype operates at 500 MHz, dissipating 117 mW at the nominal 1V VDD. Compared to the conventional design, the secure cache has an 10% area overhead, 20% power overhead at iso-performance.

Ken Mai

Papers

A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

A compact energy-efficient pseudo-static camouflaged logic family

REDAC: Distributed, Asynchronous Redundancy in Shared Memory Servers

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS