An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Advances in physics

The rapid increase in information in the big-data era calls for changes to information-processing paradigms, which, in turn, demand new circuit-building blocks to overcome the decreasing cost-effectiveness of transistor scaling and the intrinsic inefficiency of using transistors in non-von Neumann computing architectures. Accordingly, resistive switching materials (RSMs) based on different physical principles have emerged for memories that could enable energy-efficient and area-efficient in-memory computing. In this Review, we survey the four physical mechanisms that lead to such resistive switching: redox reactions, phase transitions, spin-polarized tunnelling and ferroelectric polarization. We discuss how these mechanisms equip RSMs with desirable properties for representation capability, switching speed and energy, reliability and device density. These properties are the key enablers of processing-in-memory platforms, with applications ranging from neuromorphic computing and general-purpose memcomputing to cybersecurity. Finally, we examine the device requirements for such systems based on RSMs and provide suggestions to address challenges in materials engineering, device optimization, system integration and algorithm design. Resistive switching materials enable novel, in-memory information processing, which may resolve the von Neumann bottleneck. This Review focuses on how the switching mechanisms and the resultant electrical properties lead to various computing applications.

Resistive switching materials for information processing

In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (Ion/Ioff) >; 106. For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Ferroelectrics are a class of materials that possess a variety of interactions between electrical, mechanical, and thermal properties that have enabled a wealth of functionalities. To realize integrated systems, the integration of these functionalities into semiconductor processes is necessary. To this end, the complexity of well-known ferroelectric materials, e.g., the perovskite class, causes severe issues that limit its applications in integrated systems. The discovery of ferroelectricity in hafnium oxide-based materials brought a renewed interest into this field during the last decade. Very recently, ferroelectricity was also verified in aluminum scandium nitride extending the potential of seeing a wealth of ferroelectric functions in integrated electronics in the future. This paper discusses the prospects of both material systems in various applications.

Next generation ferroelectric materials for semiconductor process integration and their applications

Analogue in-memory computing using memristors could alleviate the performance constraints imposed by digital von Neumann systems in data-intensive tasks. Conventional linear memristors typically operate at high currents, potentially limiting power efficiency and scalability in practical applications. Here, we show that nonlinear ferroelectric tunnel junction memristors can perform linear computation at ultralow currents. Using logarithmic line drivers, we demonstrate that analogue-voltage-amplitude vector–matrix multiplication (VMM) can be performed in selectorless ferroelectric tunnel junction crossbars by exploiting a device nonlinearity factor that remains constant for multiple conductive states. We also show that our ferroelectric tunnel junction crossbars have the attributes required to scale analogue VMM-intensive applications, such as neural inference engines, towards energy efficiencies above 100 tera-operations per second per watt. Nonlinear ferroelectric tunnel junction memristors can be used to perform linear vector–matrix multiplication operations at ultralow currents.

Low-power linear computation using nonlinear ferroelectric tunnel junction memristors

We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with V th tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and I on of 1mA/µm at I off of 100nA/µm is achieved. We also demonstrate V th control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.

10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V th tunability through thin BOX

We investigated the substrate bias effect in 10-nm-diameter tri-gate nanowire (NW) MOSFETs on ultrathin BOX. By employing a thin BOX of 20 nm and a thin NW body, a large body effect factor was achieved, which is sufficient for wide range Vth control. Ion-Ioff adjustment by Vsub of 1 V or -1 V enabled a 13% increase in Ion or a one-order decrease in Ioff, respectively. Negative Vsub could enlarge SRAM noise margin. Thus, a tri-gate NW MOSFET on ultrathin BOX is potential advantage for low power operation by adopting dynamic power and performance management.

Threshold Voltage Control by Substrate Bias in 10-nm-Diameter Tri-Gate Nanowire MOSFET on Ultrathin BOX

We present the recent progress in HfO 2 -based ferroelectric FET (FeFET) and ferroelectric tunnel junction (FTJ) memory towards low-power and high-density storage and AI applications. A huge amount of interface trap charges coupled to spontaneous polarization significantly alters the operating model and improvement guideline of HfO 2 FeFET irrespective of elements doped into HfO 2 . Performance and reliability of in-memory reinforcement learning (RL) with HfO 2 FTJ array are enhanced by improving the characteristics of FTJ memory cells.

HfO 2 -based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications

We systematically studied short-channel mobility (μ) in SOI nanowire transistors (NW Tr.). The strain induced in the NW channel dominates short-L μ. μ of short-L &#60;110> NW nFETs largely increases due to vertical compressive strain. We achieved further strain enhancement in NW channel by stress memorization technique (SMT). μ increase by SMT is much larger in NW Tr. than in planar Tr. In &#60;110> NW nFETs, I on on the same DIBL increases by as much as 58% by SMT thanks to significant R SD reduction in addition to μ increase, while I on degradation of pFETs is minimal.

Kensuke Ota

Papers

Low-power linear computation using nonlinear ferroelectric tunnel junction memristors

10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V th tunability through thin BOX

Threshold Voltage Control by Substrate Bias in 10-nm-Diameter Tri-Gate Nanowire MOSFET on Ultrathin BOX

HfO 2 -based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications

Understanding of short-channel mobility in tri-gate nanowire MOSFETs and enhanced stress memorization technique for performance improvement