In wireless sensor networks, the energy source is limited to the capacity of the sensor node's battery. Clustering in WSN can help with reducing energy consumption because transmission energy is related to the distance between sender and receiver. In this paper, we propose a fuzzy logic model for cluster head election. The proposed model uses five descriptors to determine the opportunity for each node to become a CH. These descriptors are: residual energy, location suitability, density, compacting, and distance from the base station. We use this fuzzy logic model in proposing the Fuzzy Logic-based Energy-Efficient Clustering for WSN based on minimum separation Distance enforcement between CHs (FL-EEC/D). Furthermore, we adopt the Gini index to measure the clustering algorithms' energy efficiency in terms of their ability to balance the distribution of energy through WSN sensor nodes. We compare the proposed technique FL-EEC/D with a fuzzy logic-based CH election approach, a k-means based clustering technique, and LEACH. Simulation results show enhancements in energy efficiency in terms of network lifetime and energy consumption balancing between sensor nodes for different network sizes and topologies. Results show an average improvement in terms of first node dead and half nodes dead.

https://www.mdpi.com/1424-8220/19/3/561/pdf

Energy-Efficient Fuzzy-Logic-Based Clustering Technique for Hierarchical Routing Protocols in Wireless Sensor Networks.

String matching has been an extensively studied research domain in the past two decades due to its various applications in the fields of text, image, signal, and speech processing. As a result, choosing an appropriate string matching algorithm for current applications and addressing challenges is difficult. Understanding different string matching approaches (such as exact string matching and approximate string matching algorithms), integrating several algorithms, and modifying algorithms to address related issues are also difficult. This paper presents a survey on single-pattern exact string matching algorithms. The main purpose of this survey is to propose new classification, identify new directions and highlight the possible challenges, current trends, and future works in the area of string matching algorithms with a core focus on exact string matching algorithms.

/pdf/exact-string-matching-algorithms-survey-issues-and-future-349jc1is6b.pdf

Exact String Matching Algorithms: Survey, Issues, and Future Research Directions

This paper proposes a new one-dimensional chaotic map, called chaotic coupled Sine map (CCSM), for the scrambling and encryption processes. The purpose of the CCSM design is to increase the security of the key space relative to the basic maps, such as Logistic map and Sine map. Bifurcation diagram and Lyapunov exponent analysis showed that the proposed map is fully chaotic and can be used as a secure pseudo-random number generator in encryption systems. Furthermore, to increase the flexibility of the proposed method, a dynamic algorithm based on the size of blocks is used in the scrambling process. To compare the proposed method and some similar schemes, a simple encryption process is used. The simulation results of this algorithm are evaluated based on security and performance analysis criteria. The comparison results show that the suggested technique has better performance in terms of security and visual quality measure.

Digital image scrambling based on a new one-dimensional coupled Sine map

Wireless Sensor Network is a wide area monitoring tools supporting for Scientific Research, Low-power microscopic sensors. WSN uses limited resource memory, computation power, bandwidth, and energy. The Cluster Routing protocol is the best methodologies for energy efficiency in the wireless sensor network. Cluster Routing Protocols are used to form a cluster creation on the selection of cluster head (CH). Then the data packets are sending from one CH to another CH and finally data packets are send to the base station. CHs are selected by using the setup phase. This system proposed a multi hop transmission, where the data packets are send from one hop to another hop. Finally these data packets are transmitted to the base station. To transmit the packets from source sensor to wireless sensor network base station via the cluster head, using the fuzzy logic type 1with three parameters such as trust factor and distance. The fuzzy logic predicts the nodes, which is having high trust factor, and near to the base station CH will be selected as best forwarder by using Type 1 fuzzy logic. It will direct to increase the life time of network plus reduce the overhead of network.

Development of Fuzzy based Energy Efficient Cluster Routing Protocol to Increase the Lifetime of Wireless Sensor Networks

This paper focuses on recognizing Arabic embedded text in videos. The proposed methods proceed without applying any prior pre-processing operations or character segmentation. Difficulties related to the video or text properties are faced using a learned robust representation of the input text image. This is performed using Convolutional Neural Networks and Deep Auto-Encoders. Features are computed using a multi-scale sliding window scheme. A connectionist recurrent approach is then used. It is trained to predict correct transcriptions of the input image from the associated sequence of features. Proposed methods are extensively evaluated on a large video database recorded from several Arabic TV channels.

Deep learning and recurrent connectionist-based approaches for Arabic text recognition in videos

This paper describes an efficient FPGA based hardware design for different image processing, enhancement, and filtering algorithms. FPGAs are often used as implementation platforms for real-time image processing applications because their structure is able to exploit spatial and temporal parallelism. The approach used is a windowing operator technique to traverse the pixels of an image, and apply the filters to them. As image sizes bit depth grow larger, software becomes less useful and real-time hardware systems are needed to take their place. The results are obtained for image size of 585×450, but the approach discussed can be used for images of any size, as long as the FPGA memory will hold it. The implementation was created with the Xilinx Spartan-6 FPGA on a Nexys3 board in mind.

Implementing image processing algorithms in FPGA hardware

This paper proposes a novel architecture for high speed combined binary/decimal addition/subtraction. We start by designing a correction-free Binary Coded Decimal (BCD) digit adder which exhibits high performance. We then use the proposed BCD digit adder to create a fast multi-digit BCD adder. The resulting multi-digit BCD adder is then used to build a combined binary/decimal addition/subtraction unit. The proposed combined binary/decimal addition/subtraction unit has been functionally verified and then implemented on Xilinx FPGA using Xilinx CAD tools. Implementation results show that our design outperforms the existing designs in terms of speed and most of the existing designs in terms of area.

Fast binary/decimal adder/subtractor with a novel correction-free BCD addition

In this paper an Arabic Optical Character Recog- nition system is implemented. The system takes a scanned image of an Arabic text as an input and generates an editable text out of it. The system starts by segmenting the document which is presented as an image into lines, then each line is also segmented into separate words, after that each word is further segmented to sub-words. Each word or sub-word is segmented into separate characters, and then a features extraction process is applied on each character to calculate its features vector. The feature vector is then compared with templates of feature vectors for each of the Arabic alphabet with their variations. The minimum distance classifier is used in the classification stage. A recognition rate of 93.5% is attained. To improve the accuracy of the system, a lookup dictionary is employed to correct some of the misclassified characters. This resulted in improving the accuracy to 96.1%. The results achieved are promising regardless that Arabic Optical Character Recognition is considered many times harder to handle than its counterparts in other languages like English due to the continuity between the letters in the same word. Index Terms—Arabic OCR, Arabic characters, Segmenta- tion, Recognition, Image processing

/pdf/automated-system-for-arabic-optical-character-recognition-1j7fsvi2ox.pdf

Automated System for Arabic Optical Character Recognition with Lookup Dictionary

Decimal arithmetic has gained high impact on the overall performance of today's financial and commercial applications. Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FPGAs provide an efficient hardware platform that can be employed for accelerating decimal algorithms. In this paper, different designs for two decimal digit adders and one decimal digit multiplier are proposed. The proposed designs were described, functionally tested, and implemented using VHDL and the Xilinx ISE 10.1 targeting Xilinx Vertix-5 XC5VLX30-3 FPGA. Implementation results and comparison with existing designs are provided.

FPGA implementation of binary coded decimal digit adders and multipliers

This paper presents efficient low-power compact hardware designs for common image processing functions including the median filter, smoothing filter, motion blurring, emboss filter, sharpening, Sobel, Roberts, and Canny edge detection. The designs were described in Verilog HDL. Xilinx ISE design suite was used for code simulation, synthesis, implementation, and chip programming. The designs were all evaluated in terms of speed, area number of LUTs and registers, and power consumption. Post placement and routing Post-PAR results show that they need very small area and consume very little power while achieving good frame per second rate even for HDTV high resolution frames. This makes them suitable for real-time applications with stringent area and power budgets.

Khaldoon Mhaidat

Papers

Implementing image processing algorithms in FPGA hardware

Fast binary/decimal adder/subtractor with a novel correction-free BCD addition

Automated System for Arabic Optical Character Recognition with Lookup Dictionary

FPGA implementation of binary coded decimal digit adders and multipliers

Efficient Low-Power Compact Hardware Units for Real-Time Image Processing