A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.

Method and system for mask optimization

Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

Methods and systems for determining a position of inspection data in design data space

An apparatus for reviewing defects including an image processing section (defect classification device section) with a function of estimating a non-defective state (reference image) of a portion in which the defect exists by use of a defect image, and a function of judging criticality or non-flat state of the defect by use of the estimation result. It becomes possible to establish both of a high-throughput image collecting sequence in which any reference image is not acquired and high-precision defect classification, and then to realize both of a high performance classifying function and a high-throughput image collecting function in a defect reviewing apparatus which automatically collects and classifies images of defects existing on a sample of a semiconductor wafer or the like.

Method and apparatus for reviewing defects

Various systems and methods for creating persistent data for a wafer and using persistent data for inspection-related functions are provided. One system includes a set of processor nodes coupled to a detector of an inspection system. Each of the processor nodes is configured to receive a portion of image data generated by the detector during scanning of a wafer. The system also includes an array of storage media separately coupled to each of the processor nodes. The processor nodes are configured to send all of the image data or a selected portion of the image data received by the processor nodes to the arrays of storage media such that all of the image data or the selected portion of the image data generated by the detector during the scanning of the wafer is stored in the arrays of the storage media.

Systems and methods for creating persistent data for a wafer and for using persistent data for inspection-related functions

Computer-implemented methods and systems for detecting defects in a reticle design pattern are provided. One computer-implemented method includes acquiring images of the reticle design pattern using a sensor disposed on a substrate arranged proximate to an image plane of an exposure system configured to perform a wafer printing process using the reticle design pattern. The images illustrate how the reticle design pattern will be projected on a wafer by the exposure system at different values of one or more parameters of the wafer printing process. The method also includes detecting defects in the reticle design pattern based on a comparison of two or more of the images corresponding to two or more of the different values.

Methods and systems for detecting defects in a reticle design pattern

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

Determining Design Coordinates for Wafer Defects

Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Pattern weakness and strength detection and tracking during a semiconductor device fabrication process

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

Pattern centric process control

The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.

Khurram Zafar

Papers

Methods and systems for utilizing design data in combination with inspection data

Determining Design Coordinates for Wafer Defects

Pattern weakness and strength detection and tracking during a semiconductor device fabrication process

Pattern centric process control

Region based virtual fourier filter