Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Pattern weakness and strength detection and tracking during a semiconductor device fabrication process

The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

Lithographic plane check for mask processing

A method for inspecting a customized orthodontic aligner for manufacturing defects, the customized orthodontic aligner customized for a specific arch of a specific patient and a specific stage of orthodontic treatment, the method including obtaining images of the customized orthodontic aligner; identifying an identifier of the customized orthodontic aligner, determining a digital file based on the identifier, the digital file associated with the customized orthodontic aligner including a digital model of a mold used during manufacture of the customized orthodontic aligner, determining a intended property for the customized orthodontic aligner by digitally manipulating the digital model of the mold, determining an actual property of the customized orthodontic aligner from the images, determining whether there is a manufacturing defect in the customized orthodontic aligner by comparing the intended property with the actual property, outputting an output associated with the determination of whether there is a manufacturing defect.

Aligner image based quality control system

Application of automation for in-line quality inspection, a zero-defect manufacturing approach

Despite great effort before design tapeout, there are still some pattern related systematic defects showing up in production,
which impact product yield. Through various check points in the production life cycle endeavor is made to detect these
defective patterns. It is seen that apart from the known defective patterns, slight variations of polygon sizes and shapes in the
known defective patterns also cause yield loss. This complexity is further compounded when interactions among multiple
process layers causes the defect. Normally the exact pattern matching techniques cannot detect these variations of the
defective patterns. With the currently existing tools in the fab it is a challenge to define the 'sensitive patterns', which are
arbitrary variations in the known 'defective patterns'. A design based approach has been successfully experimented on
product wafers to detect yield impacting defects that greatly reduces the TAT for hotspot analysis and also provides
optimized care area definition to enable high sensitivity wafer inspection.
A novel Rule based pattern search technique developed by Anchor Semiconductor has been used to find sensitive patterns in
the full chip design. This technique allows GUI based pattern search rule generation like, edge move or edge-to-edge
distance range, so that any variations of a particular sensitive pattern can be captured and flagged. Especially the pattern rules
involving multiple process layers, like M1-V1-M2, can be defined easily using this technique. Apart from using this novel
pattern search technique, design signatures are also extracted around the defect locations in the wafer and used in defect
classification. This enhanced defect classification greatly helps in determining most critical defects among the total defect
population. The effectiveness of this technique has been established through design to defect correlation and SEM
verification.
In this paper we will report details of the design based experiments that were successfully run on multiple process layers in
production device.

Yield impacting systematic defects search and management

As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity
and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect
counts pose great challenges in the post inspection defect classification and disposition: which defect is real
defect, and among the real defects, which defect should be repaired and how to verify the post-repair
defects.
In this paper, we address the challenges in mask defect verification and disposition, in particular, in post
repair defect verification by an efficient methodology, using SEM mask defect images, and optical
inspection mask defects images (only for verification of phase and transmission related defects).
We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In
total 20 types of defects were designed including defects found in typical real circuit environments with 30
different sizes designed for each type. The SEM image was taken for each programmed defect after the test
mask was made. Selected defects were repaired and SEM images from the test mask were taken again.
Wafers were printed with the test mask before and after repair as defect printability references.
A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The
software is used to extract edges from the mask SEM images and convert them into polygons to save in
GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to
form mask patterns and were merged back into the original GDSII design file. This merge is for the
purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and
accurate simulation requires including larger area of optical proximity effect. With lithography process
model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If
such complicated model is not available, a simple optical model can be used to get simulated aerial image
intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the
contour (or intensity) differences between defect pattern and normal pattern. With user provided judging
criteria, this software can be easily disposition the defect based on contour comparison. In addition, process
sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model,
which will make mask defect disposition criteria more intelligent.

/pdf/simulation-based-mask-defect-repair-verification-and-4ezc3cv7bk.pdf

Simulation based mask defect repair verification and disposition

As device features continue to shrink, achieving acceptable yields becomes increasingly challenging. In the photolithography process, mask error is one of the most critical error sources, since any imperfections on a mask will be amplified and transferred onto a wafer due to Mask Error Enhancement Factor (MEEF) [1]. Furthermore, due to complexity of lithography optical proximity effect correction in advanced technology nodes, more and more 2D structures are applied into mask patterns. Furthermore, more 2D pattern configurations are susceptible to pattering failures due to their much high MEEF factor than 1D pattern. As a result, the conventional mask error control mechanisms for 1D [2] [3] [4] only, such as mean-to-target (MTT) and CD uniformity, are no longer adequate to deal with high MEEF 2D structures. In this paper, a novel 2D structure mask error monitoring technique is introduced to prevent fatal wafer printing errors such as CD error, line-end pull back and other pattern distortions to ensure high quality mask manufacturing and to improve wafer yield in advanced technology nodes. We will demonstrate the flow using typical 2D structure test patterns in 28nm technology node design or beyond. The SEM image would be taken and measured by this novel technique are used to monitor mask fidelity performance. This monitoring technique is based on Image-to-layout, as one of Anchor Semiconductor’s pattern centric techniques, which can extract contour and convert it into pattern layouts from SEM or optical image of masks. Further pattern signature analysis can be performed on the pattern (inner /outer vertex, space distance and edge distance), so that we can quickly identify target locations for 2D pattern measurements. We monitor the severity of 2D corner rounding on selected 28nm design rule masks by Pattern Fidelity (PF) ratio and correlate them with wafer printing results. 2D pattern measurement techniques and PF ratio monitoring system from SEM image is an effective approach to ensure high quality mask making in 28nm and advanced technology nodes. This PF ratio monitoring from 2D pattern SEM images is an effective approach to ensure high quality mask making in advanced 28nm node and beyond, which can overcome the inadequacy of current 1D measurement only method, especially for the masks are generated without source mask optimization (SMO) [6].

Enhanced photomask quality control by 2D structures monitoring using auto image-to-layout method on advanced 28nm technology node or beyond

We have reported the first part of the work in 2009 BACUS meeting [1], using primarily SEM mask defect images as input. This paper is the extension of that work using mask optical inspection images with a new image process algorithm. Simulation has been widely used in overall lithography process, called computational lithography, as an effective way for cost and time reduction. As the industry moves towards 45nm and 32nm technology nodes in production, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defects are real defects, and among the real defects, which defects should be repaired and how to verify the post-repair defects. In this paper, we report simulation mask defect printability check and disposition results extending beyond SEM mask defect images [1] into optical inspection mask defects images to demonstrate cost and time reduction by simulation in mask defect management area. A new algorithm has been developed in the software tool to convert optical inspection mask defect images into “pseudo-defect” polygons in GDS format. Then, the converted defect polygons were filled with the correct tone to form mask patterns and were merged back into the original design GDS. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get aerial image intensity of AOI. With build-in contour analysis functions, the software can easily compare the contour (or intensity) differences between real mask (with defect) and normal mask (without defect). With user provided judging criteria, software can be easily disposition the defect based on contour comparison. The software has been tested and adapted for production use. We will present some accuracy test results against AIMS tool or wafer CDs in defect printability check.

Simulation Based Mask Defect Printability Verification and Disposition, Part II

Defect review is a time consuming job. Human error makes result inconsistent. The defects located on don’t care area would not hurt the yield and no need to review them such as defects on dark area. However, critical area defects can impact yield dramatically and need more attention to review them such as defects on clear area. With decrease in integrated circuit dimensions, mask defects are always thousands detected during inspection even more. Traditional manual or simple classification approaches are unable to meet efficient and accuracy requirement. This paper focuses on automatic defect management and classification solution using image output of Lasertec inspection equipment and Anchor pattern centric image process technology. The number of mask defect found during an inspection is always in the range of thousands or even more. This system can handle large number defects with quick and accurate defect classification result. Our experiment includes Die to Die and Single Die modes. The classification accuracy can reach 87.4% and 93.3%. No critical or printable defects are missing in our test cases. The missing classification defects are 0.25% and 0.24% in Die to Die mode and Single Die mode. This kind of missing rate is encouraging and acceptable to apply on production line. The result can be output and reloaded back to inspection machine to have further review. This step helps users to validate some unsure defects with clear and magnification images when captured images can’t provide enough information to make judgment. This system effectively reduces expensive inline defect review time. As a fully inline automated defect management solution, the system could be compatible with current inspection approach and integrated with optical simulation even scoring function and guide wafer level defect inspection.

Chingyun Hsiang

Papers

Pattern weakness and strength detection and tracking during a semiconductor device fabrication process

Simulation based mask defect repair verification and disposition

Enhanced photomask quality control by 2D structures monitoring using auto image-to-layout method on advanced 28nm technology node or beyond

Simulation Based Mask Defect Printability Verification and Disposition, Part II

Automatically high accurate and efficient photomask defects management solution for advanced lithography manufacture