Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor

High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

High density SRAM cell with latched vertical transistors

An oximeter uses a sigma-delta modulator and a multi-bit ADC (54) with PWM feedback (56) enabling high precision multi-bit conversion. Demodulation is done in software, thus requiring only a single hardware path for both red and IR. Multiple capacitors are switched into the integrator (44) in the sigma-delta modulator, with different capacitors for red, IR and dark signals, thus enabling the use of the single hardware path. A switching circuit (76) at the input of the sigma-delta modulator acts as a sample and hold, controlled by the PWM feedback (56).

Multi-bit ADC with sigma-delta modulation

An electronic sensor (Figure 20) is provided for detecting the presence of one or more analytes of interest in a sample. The sensor preferably comprises a field effect transistor in which conductance is enhanced by analyte binding to receptors in the active region 280. An array of sensors may be formed to analyze a sample for multiple analytes.

Ultrasensitive biochemical sensor

PURPOSE:To obtain a high-density recording medium which provides a particularly high reproduced output by providing >=2 layers of magnetic layers, incorporating ferromagnetic hexagonal ferrite powder in the outermost magnetic layer and specifying the square ratio of the hexagonal ferrite layer in the vertical direction of the magnetic recording medium at a specific value of above. CONSTITUTION:A magnetic recording medium is formed by laminating and forming >=2 layers of magnetic layers contg. pulverized ferromagnetic powder and a binder as an essential component of a nonmagnetic substrate. A magnetic coating is coated on the substrate of such recording medium in such a way that the outermost magnetic layer contains hexagonal ferrite such as BaO.6Fe2O3 or the like and a binder as an essential component and that the square ratio thereof attains >=0.7 in the vertical direction of the magnetic recording medium. The substrate is thereafter passed between the magnets provided above and below the same to orient the magnetic layer before the coating dries. Co-contg. Fe2O3, CrO2, ferromagnetic alloy powder, etc. are used for the magnetic layer under said magnetic layer. The lower magnetic layer is provided as the magnetic flux from a head is hard to form a closed loop with only the hexagonal ferrite layer in the outermost part. The high-density recording medium which is improved in the reproduced output with a ring type head is thus obtd.

Magnetic recording medium

A semiconductor switching device of field-drive type includes a bipolar component having a pnp transistor portion (8) and a npn transistor portion (9), said pnp transistor portion (8) and said npn transistor portion (9) being connected to cause a positive feedback, and a n-channel MOS transistor (11) connected across an emitter electrode (n3) and a collector electrode (n2) of said npn transistor portion (9), wherein a p-channel MOS transistor (10) is connected across an emitter electrode (p1) and a connector electrode (p2) of the pnp transistor portion (8), and a control terminal of said n-channel MOS transistor (11) is electrically connected with a control terminal of said p-channel MOS transistor (10). Said device is operable to control the main drive section even in the floating state and to drive the main drive section by a small control current.

Semiconductor switch circuit

PURPOSE: To limit the range of the output amplitude of an integrator, to improve the S/N characteristic of an output from the integrator and to give a margin to an integration characteristic by providing adders adding an input signal to an integration signal, apperantly integrating the input signal and permitting the integrator to simultaneously integrate the input and feedback. CONSTITUTION: When the input signal Vin is given to the adders 90 and 91, the adder 90 takes the difference between the input signal and a feedback signal from an encoder 94, and the integrator 91 integrates the difference. The output of the integrator 91 is given to the other adder 92. It addes the output of the integrator 91 and the input signal Vin, and gives the added output to a quantizer 93. It decides (quantizes) the polarity of the output of the adder 92, outputs a binary output signal Do corresponding to the polarity, and simultaneously gives said signal to a decoder 94. It decodes the output signal of the quantizer 93 to an analog signal, generates the feedback signal, and negatively feeds back said signal to the adder 90. Namely, the adder 92 adds the input signal Vin and the output of the integrator 91, which is apperantly equal to the integration of the input signal Vin. COPYRIGHT: (C)1988,JPO&Japio

Delta/sigma type a/d converter

PURPOSE:To compensate the gain reduction at a high frequency part by provid ing a 2nd differential amplifier (DA) in addition to a 1st DA comprising two sets of amplification transistors (TRs), a buffer TR and a load circuit and crossing outputs of the 2nd DA to drive the buffer TR. CONSTITUTION:The amplifier TR Q1, the buffer TR QB1, a load resistor L1, and the TRs Q2, QB2 and a resistor L2 are connected respectively in series to form the 1st DA, which is connected to power lines E1, E2 via a constant current source H1. The 1st DA receives a signal from input lines M1, M2 and gives an output from output lines T1, T2. The 2nd DA consists of the amplifier TRs Q3, Q4 and the load resistors L3, L4 and is connected to the power lines E1, E2 via a constant current source H2 and a resistor 5. The 2nd DA uses the input lines M1, M2 of the 1st DA in common and crosses outputs from the loads L3, L4 to apply the result to gates of the buffer TRs QB2, QB1 of the 1st DA. Thus, even when the frequency of the input signal is higher, the output is not decreased and the frequency characteristic is improved.

Differential amplifier circuit

PURPOSE: To attain multiplexing of a quantization loop by providing a sample- and-hold circuit, an input changeover switch and a storage circuit. CONSTITUTION: A switch 100 switching an input signal Vin and an output of a sample-and-hold circuit, an input adder 101, an integration device 102 having plural (N) number of integration capacitors Ci1∼CiN switched a t a prescribed timing, an adder 103, and a quantizer (Q) 104 comprising an A/D converter or the like are provided and they are connected sequentially in series. The input of one adder 101 is connected to the other adder 103. A decoder 105 com prising a D/A converter or the like generating a feedback signal is connected between the output of the quantizer 104 and the adder 101 and a sample-and-hold circuit 106 sampling the output of the integrator and holding the result is con nected between the switch 100 and the output of the integration device 102. Further, the storage circuit 107 storing sequentially the output of the quantizer is connected to the output side of the quantizer 104 and a differentiation circuit 108 and the adder 109 are connected to the output side of the storage circuit 107. COPYRIGHT: (C)1987,JPO&Japio

Multiplex dela sigma (deltasigma) type analog-digital converter

PURPOSE:To prevent the change of a rise time of an optical pulse output by a method wherein a voltage difference between base voltages given to a first and second transistors of a pulse current supply circuit respectively is made to change corresponding to the temperature change of a laser diode. CONSTITUTION:A voltage between a base and an emitter of each of transistors(Trs) 22 and 23 and Trs used in the circuits 12 and 12' and a voltage between the ends of each of diodes 19 and 19' have a negative temperature dependency and the emitter area of a Tr 16' of the circuit 12' is made sufficiently larger than that of Tr 23 and a current almost equal to that of a constant current source 21 is made to flow through the Tr 16', where by voltage difference between voltages given to the bases of Trs 13 and 13' from base voltage generating circuits 12 and 12' of a pulse current supply circuit is made to have a positive temperature dependency. Therefore, a current pulse Ip supplied to a laser diode 1 from a circuit 6 is made to have a positive temperature dependency, so that even if the laser diode 1 changes in temperature, a light pulse whose rise time is kept constant can be projected from the laser diode 1.

Kimura Tadakatsu

Papers

Semiconductor switch circuit

Delta/sigma type a/d converter

Differential amplifier circuit

Multiplex dela sigma (deltasigma) type analog-digital converter

Laser diode drive circuit