K
Kishor Sarawadekar
Researcher at Indian Institute of Technology (BHU) Varanasi
Publications - 47
Citations - 293
Kishor Sarawadekar is an academic researcher from Indian Institute of Technology (BHU) Varanasi. The author has contributed to research in topics: Gesture & JPEG 2000. The author has an hindex of 7, co-authored 39 publications receiving 182 citations. Previous affiliations of Kishor Sarawadekar include Xilinx & Indian Institute of Technology Kharagpur.
Papers
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Proceedings ArticleDOI
Polynomial Learning Rate Policy with Warm Restart for Deep Neural Network
TL;DR: Another warm restart technique which is inspired by cyclical learning rate and stochastic gradient descent with warm restarts is introduced and it uses “poly” LR policy which helps in faster convergence of the DNN and it has slightly higher classification accuracy.
Journal ArticleDOI
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000
TL;DR: To encode all samples in a stripe-column, concurrently a new technique named as compact context coding is devised, and high throughput is attained and hardware requirement is also cut down.
Journal ArticleDOI
Towards hand gesture based writing support system for blinds
TL;DR: A new dactylology is proposed to achieve functionality similar to a standard keyboard and a new feature extraction technique called as reduced shape signature (RSS), which is rotation, translation and scale invariant is introduced.
Journal ArticleDOI
An Optimized Architecture of HEVC Core Transform Using Real-Valued DCT Coefficients
TL;DR: A new transform kernel for HEVC is proposed which uses a new set of real-valued DCT coefficients which reduces the hardware cost and the processing time by reducing the complexity as well as intermediate data length.
Journal ArticleDOI
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000
TL;DR: Relative figure of merit is computed to compare the overall efficiency of all architectures which show that the proposed architecture provides good balance between the throughput and hardware cost.