K
Korbin S. Van Dyke
Researcher at Advanced Micro Devices
Publications - 34
Citations - 2095
Korbin S. Van Dyke is an academic researcher from Advanced Micro Devices. The author has contributed to research in topics: Instruction set & State (computer science). The author has an hindex of 21, co-authored 34 publications receiving 2095 citations. Previous affiliations of Korbin S. Van Dyke include Hastings Entertainment.
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Patent
Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
TL;DR: The branch prediction cache (BPC) as mentioned in this paper provides a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address.
Patent
Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
Harold L. McFarland,David R. Stiles,Korbin S. Van Dyke,Shrenik Mehta,John G. Favor,Dale R. Greenley,Robert A. Cargnoni +6 more
TL;DR: In this paper, a pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to functional units, with up to n operations allowed to be outstanding.
Patent
Two-level branch prediction cache
TL;DR: An improved branch prediction cache (BPC) as mentioned in this paper utilizes a hybrid cache structure that provides two levels of branch information caching, a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions.
Patent
Apparatus for executing programs for a first computer architechture on a computer of a second architechture
TL;DR: In this paper, the authors propose a set of entry exceptions, called entry exception, exit exception, entry handler, and resumption exception, which are cooperatively designed to maintain an association between a thread and an extended context of the thread through context change induced by the operating system.
Patent
Configurable branch prediction for a processor performing speculative execution
TL;DR: In this article, a branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated, programmatically in software or by hardware in response to processor events.