Patent
Two-level branch prediction cache
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TLDR
An improved branch prediction cache (BPC) as mentioned in this paper utilizes a hybrid cache structure that provides two levels of branch information caching, a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions.Abstract:
An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.read more
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References
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Patent
System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
TL;DR: In this article, a super-scaler processor with branch-prediction information is described, where each instruction cache block stored in the instruction cache memory includes branch prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within an instruction block.
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Streamlined instruction processor
Gigy Baror,Brian Case,Rod Fleck,Philip M. Freidin,Smeeta Gupta,William M. Johnson,Cheng-Gang Kong,Ole Moller,Timothy Alan Olson,David I. Sorensen +9 more
TL;DR: In this article, a streamlined instruction processor is proposed to process data in response to a program composed of prespecified instructions in pipeline cycles, which includes an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory.
Patent
Pageable branch history table
James Herbert Pomerene,Thomas R. Puzak,Rudolph Nathan Rechtschaffen,Philip Lewis Rosenfeld,Frank John Sparacio +4 more
TL;DR: In this article, a branch history table (BHT) is divided into two parts: an active area (131) and a backup area (136), where the active area contains entries for a small number of branches which the processor can encounter in the near future and the back up area contains all other branch entries.
Patent
System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
TL;DR: In this article, a delayed-branch instruction processor is proposed, which treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register.
Patent
Instruction prefetching device comprising a circuit for checking prediction for a branch instruction before the instruction is executed
TL;DR: In this article, a data processing system capable of processing instructions under pipeline control in a plurality of stages including an executing stage, an instruction prefetching device comprises a prediction checking circuit (66, 67) coupled to a predicting circuit (52, 53) and an instruction executing circuit (32, 33, 37, 38) and a prefetch controlling circuit (47, 86).