ion and Compositional Techniques From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 E.Allen Emerson, Richard J. Trefler Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Dirk W. Hoffmann, Thomas Kropf Abstract BDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong WangBDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong Wang Theorem Proving Related Approaches Formal Synthesis at the Algorithmic Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Christian Blumenröhr, Viktor Sabelfeld Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving . . . . . 202 Mark Aagaard, Thomas Melham, John O’Leary Verification of Infinite State Systems by Compositional Model Checking . . 219 K.L.McMillan Symbolic Simulation/Symbolic Traversal Formal Verification of Designs with Complex Control by Symbolic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Gerd Ritter, Hans Eveking, Holger Hinrichsen Hints to Accelerate Symbolic Traversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Kavita Ravi, Fabio Somenzi Specification Languages and Methodologies Modeling and Checking Networks of Communicating Real-Time Processes . 265 Jürgen Ruf, Thomas Kropf ”Have I Written Enough Properties?” A Method of Comparison between Specification and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Sagi Katz, Orna Grumberg, Danny Geist Program Slicing of Hardware Description Languages . . . . . . . . . . . . . . . . . . . . 298 E.Clarke, M.Fujita, S.P.Rajan, T.Reps, S.Shankar, T.Teitelbaum Table of

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Correct Hardware Design and Verification Methods

This paper sheds light on the least-square (LS)-based adaptive prediction schemes for lossless compression of natural images. Our analysis shows that the superiority of the LS-based adaptation is due to its edge-directed property, which enables the predictor to adapt reasonably well from smooth regions to edge areas. Recognizing that LS-based adaptation improves the prediction mainly around the edge areas, we propose a novel approach to reduce its computational complexity with negligible performance sacrifice. The lossless image coder built upon the new prediction scheme has achieved noticeably better performance than the state-of-the-art coder CALIC with moderately increased computational complexity.

Edge-directed prediction for lossless compression of natural images

Apart from the existing technology on image compression represented by series of JPEG, MPEG and H.26x standards, new technology such as neural networks and genetic algorithms are being developed to explore the future of image coding. Successful applications of neural networks to vector quantization have now become well established, and other aspects of neural network involvement in this area are stepping up to play significant roles in assisting with those traditional technologies. This paper presents an extensive survey on the development of neural networks for image compression which covers three categories: direct image compression by neural networks; neural network implementation of existing techniques, and neural network based technology which provide improvement over traditional algorithms.

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Image compression with neural networks } A survey

Reprogrammable systems based on field programmable gate arrays are revolutionizing some forms of computation and digital logic. As a logic emulation system, they provide orders of magnitude faster computation than software simulation. As a custom-computing machine, they achieve the highest performance implementation for many types of applications. As a multimode system, they yield significant hardware savings and provide truly generic hardware. In this paper, we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems. In the mid-1980's, a new technology for implementing digital logic was introduced: the field programmable gate array (FPGA). These devices could be viewed as either small, slow gate arrays (MPGA's) or large, expensive programmable logic devices (PLD's). FPGA's were capable of implementing significantly more logic than PLD's, espe- cially because they could implement multilevel logic, while most PLD's were optimized for two-level logic. Although they did not have the capacity of MPGA's, they also did not have to be custom fabricated, greatly lowering the costs for low-volume parts and avoiding long fabrication delays. While many of the FPGA's were configured by static random access memory (SRAM) cells in the array, this was generally viewed as a liability by potential customers who worried over the chip's volatility. Antifuse-based FPGA's also were developed and for many applications were much more attractive, both because they tended to be smaller and faster due to less programming overhead and because there was no volatility to the configuration. In the late 1980's and early 1990's, there was a growing realization that the volatility of SRAM-based FPGA's was not a liability but was in fact the key to many new types of applications. Since the programming of such an FPGA could be changed by a completely electrical process, much as a standard processor can be configured to run many programs, SRAM-based FPGA's have become the work- horse of many new reprogrammable applications. Some uses of reprogrammability are simple extensions of the standard logic implementation tasks for which the FPGA's were originally designed. An FPGA plus several different configurations stored in read-only memory (ROM) could be used for multimode hardware, with the functions on the chip changed in reaction to the current demands. Also, boards constructed purely from FPGA's, microcontrollers, and other reprogrammable parts could be truly generic hardware, allowing a single board to be reprogrammed to serve many different applications.

The Roles of FPGA's in Reprogrammable Systems

This paper describes a new type of evolvable hardware (EHW). While most EHW research employs hardware evolution at the level of primitive gates (i.e. gate-level evolution), our alternative synthesizes hardware circuits with higher-level functions. We call this evolution "function-level evolution". In this paper, two applications of function-level EHW are described. One is for adaptive equalization in digital mobile communication; the other is for lossy data compression.

Evolvable hardware at function level

Lossless Image Compression by Two-Dimensional Linear Prediction with Variable Coefficients

A mean-square-error analysis of the steady-state coefficient fluctuation of an infinite impulse response (IIR) adaptive notch filter, whose coefficients are estimated by simple gradient and sign gradient algorithms, is presented. Regarding the magnitude and phase responses of the transfer function that is used to realize a second-order IIR adaptive notch filter, it is shown that the filter-coefficient estimation error can be studied by using first-order ordinary difference equations with stochastic input. Simple closed-form results are derived for the mean-square error of the steady-state coefficients. The results of computer experiments are presented to substantiate the analysis. >

Mean-squared error analysis of an adaptive notch filter

This paper presents the EXMalgorithm, which locates multiple logic design errors in a combinational circuit with multiple output. An error possibility index and a six-valued simulation method have been introduced to reduce the number of error candidates without missing real errors. Experimental results have shown that this algorithm locates all errors at high hit ratio for benchmark circuits.

Rectification of Multiple Logic Design Errors in Multiple Output Circuits

Two different approaches are proposed in this paper for the design of bandpass/bandstop filters with independent tunning of the center (notch) angular frequency ω 0 and the 3-dB attenuation (notch) bandwith Ω c . These approaches lead to a variety of two-multiplier structures for the realization of second-order bandpass/bandstop digital filters in which one multiplier controls ω 0 and the other multiplier adjusts Ω c

Design of Digital Bandpass/Bandstop Filters with Independent Tuning Characteristics

Explicit expressions of transfer functions for digital tan filters with low-pass, high-pass, band-pass, and band-stop characteristics approximating given design specifications are advanced. The higher order transfer function satisfying the design specification is expressed as the product of first-order and second-order filter sections of identical forms but with different coefficient values. All coefficients of these low-order filter sections are expressed in explicit forms related simply to the specification values. Thus, the result developed can be easily applied for the cascade or time-sharing realization. The low-order filter section developed here can be implemented with the fewest multipliers. The design formulae for Butterworth, Chebyshev, inverse Chebyshev and elliptic approximations are included. The transfer functions for all these filters are expressed in the same form of low-order filter section with different coefficient values.

Kotaro Hirano

Papers

Lossless Image Compression by Two-Dimensional Linear Prediction with Variable Coefficients

Mean-squared error analysis of an adaptive notch filter

Rectification of Multiple Logic Design Errors in Multiple Output Circuits

Design of Digital Bandpass/Bandstop Filters with Independent Tuning Characteristics

Explicit design formulae for digital tan filters with low-pass, high-pass, band-pass, and band- stop characteristics