This paper presents the ZUMA open FPGA overlay architecture. It is an open-source, cross-compatible embedded FPGA architecture that is intended to overlay on top of an existing FPGA, in essence an "FPGA-on-an-FPGA." This approach has a number of benefits, including bit stream compatibility between different vendors and parts, compatibility with open FPGA tool flows, and the ability to embed some programmable logic into systems on FPGAs without the need for releasing or recompiling the master net list. These options can enhance design possibilities and improve designer productivity. Previous attempts to map an FPGA architecture into a commercial FPGA have had an area penalty of 100x at best. Through careful architectural and implementation choices to exploit low-level elements of the host architecture, ZUMA reduces this penalty to as low as 40x. Using the VTR (VPR6) academic tool flow, we have been able to compile the entire MCNC benchmark suite to ZUMA. We invite authors of other tool flows to target ZUMA.

https://www.ece.ubc.ca/~lemieux/publications/brant-fccm2012.pdf

ZUMA: An Open FPGA Overlay Architecture

Cloud providers such as Amazon and Microsoft have begun to support on-demand FPGA acceleration in the cloud, and hardware vendors will support FPGAs in future processors. At the same time, technology advancements such as 3D stacking, through-silicon vias (TSVs), and FinFETs have greatly increased FPGA density. The massive parallelism of current FPGAs can support not only extremely large applications, but multiple applications simultaneously as well.System support for FPGAs, however, is in its infancy. Unlike software, where resource configurations are limited to simple dimensions of compute, memory, and I/O, FPGAs provide a multi-dimensional sea of resources known as the FPGA fabric: logic cells, floating point units, memories, and I/O can all be wired together, leading to spatial constraints on FPGA resources. Current stacks either support only a single application or statically partition the FPGA fabric into fixed-size slots. These designs cannot efficiently support diverse workloads: the size of the largest slot places an artificial limit on application size, and oversized slots result in wasted FPGA resources and reduced concurrency.This paper presents AMORPHOS, which encapsulates user FPGA logic in morphable tasks, or Morphlets. Morphlets provide isolation and protection across mutually distrustful protection domains, extending the guarantees of software processes. Morphlets can morph, dynamically altering their deployed form based on resource requirements and availability. To build Morphlets, developers provide a parameterized hardware design that interfaces with AMORPHOS, along with a mesh, which specifies external resource requirements. AMORPHOS explores the parameter space, generating deployable Morphlets of varying size and resource requirements. AMORPHOS multiplexes Morphlets on the FPGA in both space and time to maximize FPGA utilization.We implement AMORPHOS on Amazon F1 [1] and Microsoft Catapult [92]. We show that protected sharing and dynamic scalability support on workloads such as DNN inference and blockchain mining improves aggregate throughput up to 4× and 23× on Catapult and F1 respectively.

/pdf/sharing-protection-and-compatibility-for-reconfigurable-40cf9hqd0c.pdf

Sharing, protection, and compatibility for reconfigurable fabric with Amorphos

FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1)Resource level, 2)Node level, and 3)Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

/pdf/a-survey-on-fpga-virtualization-ew6kojr5kq.pdf

A Survey on FPGA Virtualization

Recent advances in artificial intelligence have been driven by an exponential growth in digitised data. Natural language processing, in particular, has been transformed by machine learning models such as OpenAI’s GPT-3 which generates human-like text so realistic that its developers have warned of the dangers of its misuse. In recent months OpenAI released Codex, a new deep learning model trained on Python code from more than 50 million GitHub repositories. Provided with a natural language description of a programming problem as input, Codex generates solution code as output. It can also explain (in English) input code, translate code between programming languages, and more. In this work, we explore how Codex performs on typical introductory programming problems. We report its performance on real questions taken from introductory programming exams and compare it to results from students who took these same exams under normal conditions, demonstrating that Codex outscores most students. We then explore how Codex handles subtle variations in problem wording using several published variants of the well-known “Rainfall Problem” along with one unpublished variant we have used in our teaching. We find the model passes many test cases for all variants. We also explore how much variation there is in the Codex generated solutions, observing that an identical input prompt frequently leads to very different solutions in terms of algorithmic approach and code length. Finally, we discuss the implications that such technology will have for computing education as it continues to evolve, including both challenges and opportunities.

/pdf/the-robots-are-coming-exploring-the-implications-of-openai-2wyp0mj7.pdf

The Robots Are Coming: Exploring the Implications of OpenAI Codex on Introductory Programming

With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits Researchers previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an FPGA The JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom FPGA fabric designed specifically for JIT compilation While developing a custom FPGA may be feasible for some applications, we propose implementing the simple FPGA fabric as a virtual FPGA In this paper, we present a virtual FPGA, described using structural VHDL and thus representing a firm core that a designer can synthesize onto an existing FPGA We synthesized the firm-core virtual FPGA onto Xilinx Spartan physical FPGAs and then mapped 18 benchmark circuits onto the virtual FPGA Our results show a 6X decrease in performance and 100x more hardware resource usage, for the virtual FPGA approach compared to mapping the circuits directly to the physical FPGA fabric While the hardware overhead is large, large commercial FPGA capacities may still mean that some applications can utilize a virtual FPGA approach if portability is more important than resource utilization Furthermore, our work provides a baseline for future virtual FPGA approaches that may reduce the performance or area overhead through various means

Firm-core virtual FPGA for just-in-time FPGA compilation

Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits. We previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an FPGA. Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom FPGA fabric designed specifically for JIT compilation. While directly implementing a custom FPGA fabric on silicon may be feasible for some applications, we investigated the option of implementing the simple FPGA fabric as a circuit mapped to a physical FPGA - a virtual FPGA. We described our simple fabric in structural VHDL, synthesized the fabric onto a Xilinx Spartan-IIE FPGA, and mapped 18 benchmark circuits onto the resulting virtual FPGA. Our results show a 6X decrease in performance and a 100X increase in hardware resource usage for the virtual FPGA approach compared to mapping the circuits directly to the physical FPGA. For applications in which hardware portability is essential, a designer could leverage the large capacity of current commercially available FPGAs to implement a virtual FPGA with tens of thousands of configurable gates, providing about the same amount of configurable logic as FPGAs produced in the mid 1990s. Nevertheless, the large overheads clearly indicate the need to develop a virtual FPGA approach tuned to physical fabrics in order to reduce the overhead.

Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only)

Modern program auto-graders enable new CS1 approaches. Instructors can easily create new assignments, with students receiving immediate score feedback and resubmitting assignments. With such auto-graders, one approach assigns many small programs (MSPs) each week instead of one large program (OLP). Earlier research showed MSPs in CS1 yielded happier students and better grades. Our university and other schools have switched to MSPs in CS1. This paper addresses common questions about MSPs. We analyzed submissions for a 76-student section of our MSP CS1 course. Given 7 MSPs per week each worth 10 points, students needed 50 points for full credit. Students averaged 17 minutes per MSP and 120 minutes per week. Given 7 days, students on average started 2.2 days ahead of the due date, with 37% starting at least 3 days ahead. 40% of students exceeded the required 50 points per week (no extra credit was given). 50% of students "pivoted" -- switching to another program before completing the previous one. 54% used MSPs to study for exams. Students used MSPs in ways beneficial to their learning and stress reduction: spending sufficient time, completing more than necessary, preparing for exams, and pivoting to avoid getting stuck. A common concern is that MSP CS1 students will do poorly in a CS2 using OLPs. We analyzed 5 quarters of CS2 and found MSP students do fine (in fact slightly better). These results encourage use and refinement of MSPs in CS1 and other courses.

An Analysis of Using Many Small Programs in CS1

In 2017, we introduced a teaching method called many small programs (MSPs) in the CS1 courses at our university. Instead of teaching via one large programming assignment (OLP) each week, MSPs allow the instructor to assign multiple programming assignments, for example 5 or more, each week instead. Our previous studies have shown that MSPs can improve the student experience by reducing stress and increasing student satisfaction in the course. Furthermore, MSPs have been shown to improve student grade performance in CS1, especially on the coding portion of exams. In a follow-up study, we gained insight on how students were using MSPs, and learned that students use MSPs in ways beneficial to their learning. Students spend sufficient time working on MSPs each week, start working on MSPs earlier, complete more MSPs than required (given a weekly full-credit threshold), take advantage of pivoting (switch to another program if stuck on the current one), and use MSPs more to study for exams. We have shared these findings with universities around the nation; causing other universities to switch from teaching CS1 with OLPs to MSPs. Given data on student MSP submissions from other schools, we extend our work to include MSPs taught at other universities. We perform similar analysis and found that students being taught via MSPs from other universities also use MSPs in beneficial ways. Students spend sufficient time working on MSPs each week, they start working on MSPs early, and they complete a majority of assigned MSPs each week.

Kris Miller

Papers

Firm-core virtual FPGA for just-in-time FPGA compilation

Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only)

An Analysis of Using Many Small Programs in CS1

Many Small Programs in CS1: Usage Analysis from Multiple Universities