Scan-based manufacturing test of low power designs often exceeds the very tight functional constraints on average and instantaneous logic switching. The logic activity during the shift and launch-capture of test pattern data may lead to excessive power consumption and voltage droop. This paper focuses on the management of instantaneous power during the capture phase. By taking advantage of the existing clock gating circuitry and selectively holding the value of some scan flip-flops, switching activity during the capture cycles of a test can be reduced. The effectiveness of this technique is demonstrated on several industrial designs that show up to 30% (55%) reduction in instantaneous (average) capture switching.

Capture power reduction using clock gating aware test generation

In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity around each long path sensitized by a test vector is checked to characterize it as hot (with excessively-high switching activity), warm (with normal/functional switching activity), or cold (with excessively-low switching activity). Then, X-restoration/X-filling-based rescue is conducted on the test vector to reduce switching activity around hot paths. If the rescue is insufficient to turn a hot path into a warm path, mask is then conducted on expected test response data to instruct the tester to ignore the potentially-false test response value from the hot path, thus achieving guaranteed capture power safety. Finally, X-restoration/X-filling-based warm-up is conducted on the test vector to increase switching activity around cold paths for improving their small-delay test capability. This novel approach of pinpoint capture power management has significant advantages over the conventionalapproachofglobalcapturepower management, as demonstrated by evaluation results on large ITC'99 benchmark circuits and detailed path delay analysis.

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On pinpoint capture power management in at-speed scan test generation

Excessive power dissipation caused by large amount of switching activities has been a major issue in scan-based testing. For large designs, the excessive switching activities during launch cycle can cause severe power droop, which cannot be recovered before capture cycle, rendering the at-speed scan testing more susceptible to the power droop. In this paper, we present a methodology to avoid power droop during scan capture without compromising at-speed test coverage. It is based on the use of a low area overhead hardware controller to control the clock gates. The methodology is ATPG (Automatic Test Pattern Generation)-independent, hence pattern generation time is not affected and pattern manipulation is not required. The effectiveness of this technique is demonstrated on several industrial designs.

A clock-gating based capture power droop reduction methodology for at-speed scan testing

At-speed or even faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable for lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak-power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose design for testability (DfT) support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner; we develop three different DfT mechanisms, one for launch-off shift, one for launch-off capture, and one for mixed at-speed testing. The proposed DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design-flow-compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering the launch/capture power.

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing

This paper describes the challenges of testing low-power designs that use the commonly used multi-supply multi-voltage (MSMV) and power shut-off (PSO) design methodology. We describe a novel solution to address the manufacturing test of an MSMV/PSO design by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology. We provide experimental results and future directions for power-aware test.

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.

SmartScan - Hierarchical test compression for pin-limited low power designs

Test Compression ratios are currently stalled at 100–200X. A new 2-dimensional physically-aware sequential Compressor-Decompressor design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest compression ratios. Results on some commonly used industrial designs shows a 2X reduction in routing overhead and congestion associated with Test Compression logic. The target test coverage is maintained while achieving up to 3.7X reduction in test data volume and test application time beyond the conventional methods.

Advancing test compression to the physical dimension

A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Krishna Chakravadhanula

Papers

Capture power reduction using clock gating aware test generation

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

SmartScan - Hierarchical test compression for pin-limited low power designs

Advancing test compression to the physical dimension

Method and apparatus for low-pin count testing of integrated circuits