다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

As of date many NBTI models have been published which aim to successfully capture the essential physics. As such, these models have mostly focused on the stress phase. The relaxation phase, on the other hand, has not received as much attention, possibly because of the contradictory results published so far. Particularly noteworthy are the very long relaxation tails of almost logarithmic nature, which cannot be successfully described by the reaction-diffusion model. The authors argue that understanding the nature of the relaxation phase could hold the key to unraveling the underlying NBTI mechanism. In particular, the authors stipulate that the relaxation phase follows a universal relaxation law, demonstrate the valuable consequences resulting therefrom, and use this universality to classify presently available NBTI models.

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The Universality of NBTI Relaxation and its Implications for Modeling and Characterization

Negative bias temperature instability (NBTI) is one of the most critical device reliability issues in sub-130 nm CMOS processes. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using a delay-locked loop (DLL), in which the increase in pMOS threshold voltage due to NBTI stress is translated into a control voltage shift in the DLL for high sensing gain. The proposed sensor is capable of supporting both DC and AC stress modes. Measurements from a test chip fabricated in a 130 nm bulk CMOS process show an average gain of 10 in the operating range of interest, with measurement times in tens of microseconds possible for minimal unwanted threshold voltage recovery. NBTI degradation readings across a range of operating conditions are presented to demonstrate the flexibility of this system.

An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation

Negative Bias Temperature Instability (NBTI) is one of the most critical device reliability issues facing scaled CMOS technology. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using two delay-locked loops (DLL). The increase in PMOS transistor threshold due to NBTI stress is translated into the control voltage of a DLL for high sensing gain. Measurements from a 0.13 μm test chip show a maximum gain of 16X in the operating range of interest, with microsecond order measurement times for minimal unwanted recovery. The proposed NBTI sensor also supports various DC and AC stress modes.

An on-chip NBTI sensor for measuring PMOS threshold voltage degradation

This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

A Review on the ESD Robustness of Drain-Extended MOS Devices

A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

Fin diode structure

ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-µm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.

/pdf/esd-protection-design-with-lateral-dmos-transistor-in-40-v-2aqh4an65a.pdf

ESD protection design with lateral DMOS transistor in 40-V BCD technology

The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

ESD protection circuit and ESD protection device thereof

Downstream Electromigration (EM) was studied on different multiple via structures. Structures with more via gained better EM performance improvement. Failure analysis showed different EM failure modes on these structures. Finite element analysis is applied to find out the current density profiles and their variation between these structures. Resistance increases due to EM induced void are also simulated and found to be dependent on size and location of void. The different EM results of these multiple via structures are explained with the current density results and the different diffusion patterns found.

Effect of multiple via layout on electromigration performance and current density distribution in copper interconnect

An electrostatic discharge (ESD) protection circuit with silicon-controlled-rectifier (SCR) device has been designed without latch-up risk. After fabrication in a 0.13-µm CMOS process, the ESD protection circuit with SCR width of 60µm can sustain 6.2kV human-body-model (HBM) and 475V machine model (MM) ESD tests. The latch-up test shows the immunity against 500-mA triggering current under 3.3V supply voltage.

Kuan-Cheng Su

Papers

Fin diode structure

ESD protection design with lateral DMOS transistor in 40-V BCD technology

ESD protection circuit and ESD protection device thereof

Effect of multiple via layout on electromigration performance and current density distribution in copper interconnect

Latch-up free ESD protection design with SCR structure in advanced CMOS technology