Atomic layer deposition: an overview.

Atomic layer deposition (ALD) is gaining attention as a thin film deposition method, uniquely suitable for depositing uniform and conformal films on complex three-dimensional topographies. The deposition of a film of a given material by ALD relies on the successive, separated, and self-terminating gas–solid reactions of typically two gaseous reactants. Hundreds of ALD chemistries have been found for depositing a variety of materials during the past decades, mostly for inorganic materials but lately also for organic and inorganic–organic hybrid compounds. One factor that often dictates the properties of ALD films in actual applications is the crystallinity of the grown film: Is the material amorphous or, if it is crystalline, which phase(s) is (are) present. In this thematic review, we first describe the basics of ALD, summarize the two-reactant ALD processes to grow inorganic materials developed to-date, updating the information of an earlier review on ALD [R. L. Puurunen, J. Appl. Phys. 97, 121301 (2005)], and give an overview of the status of processing ternary compounds by ALD. We then proceed to analyze the published experimental data for information on the crystallinity and phase of inorganic materials deposited by ALD from different reactants at different temperatures. The data are collected for films in their as-deposited state and tabulated for easy reference. Case studies are presented to illustrate the effect of different process parameters on crystallinity for representative materials: aluminium oxide, zirconium oxide, zinc oxide, titanium nitride, zinc zulfide, and ruthenium. Finally, we discuss the general trends in the development of film crystallinity as function of ALD process parameters. The authors hope that this review will help newcomers to ALD to familiarize themselves with the complex world of crystalline ALD films and, at the same time, serve for the expert as a handbook-type reference source on ALD processes and film crystallinity.

Crystallinity of inorganic films grown by atomic layer deposition: Overview and general trends

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, and for the first time the “Z-interference” between adjacent vertical layers is studied. The proposed buried-channel VG NAND allows better X, Y pitch scaling and is a very attractive candidate for ultra high-density 3D stackable NAND Flash.

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory

A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

A bandgap engineered SONOS with greatly improved reliability properties is proposed This concept is demonstrated by a multilayer structure of O1/N1/O2/N2/O3, where the ultra-thin "O1/N1/O2" serves as a non-trapping tunneling dielectric, N2 the high-trapping-rate charge storage layer, and O3 the blocking oxide The ultra-thin "O1/N1/O2" provides a "modulated tunneling barrier" - it suppresses direct tunneling at low electric field during retention, while it allows efficient hole tunneling erase at high electric field due to the band offset Therefore, this BE-SONOS offers fast hole tunneling erase, while it is immune to the retention problem of the conventional SONOS With a N+-poly gate, we achieve self-convergent erased Vt ~3 V, suitable for NOR flash application On the other hand, by using a P+-poly gate, a depletion mode device (Vt 6 V) is achieved, ideal for MLC-NAND application Excellent performance and reliability for both applications are demonstrated Furthermore, with this simple structure and no new materials BE-SONOS is readily manufacturable

BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability

Sub-30nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory window is also larger than the bulk planar devices due to the tri-gate structure that enhances the electric field during programming/erasing. However, a fair percentage of devices contain grain boundaries with poorer S.S. and g m . Interestingly, this only affects the DC characteristics but does not impact the memory window. Furthermore, grain boundaries do not increase the random telegraph noise. The most serious drawback of grain boundaries is the impact on self-boosting window caused by junction leakage. A sub-30 nm TFT BE-SONOS NAND device with MLC capability and good retention is demonstrated

Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first &#60; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Kuang-Chao Chen

Papers

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability

Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)