A survey is given of the recent literature on 1/ f noise. Proposals for mathematical models, for empirical relations and for physical models are discussed. The present situation is evaluated and some unsolved problems are indicated.

1/f noise

Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements. >

A physics-based MOSFET noise model for circuit simulators

Publisher Summary This chapter discusses the flicker noise in electronic devices. The name “flicker noise” refers to the noise phenomena with a spectrum of the form AIβ/ƒɣ, here A is a constant, I is the current, ƒ is the frequency, and the exponents β and γ are also constants. The exponent β often has a value of about 2, though deviations are not uncommon. The theory of flicker noise as suppressed emission fluctuations cannot be valid, for in that case R, would be independent of d. Flicker partition noise indicates that the rate at which the current divides between the positive electrodes is randomly modulated by a I/ƒ-type process. The noise is due to fluctuations in the surface recombination velocity s and that there is direct experimental evidence in favor of it.

Flicker Noise in Electronic Devices

DRAM cells and arrays of cells on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trench sidewalls with word lines and bit lines crossing over the cells.

Vertical DRAM cell and method

Shallow (<0.2 μm) n+ layers in Si with high conductivity (<40 Ω/⧠) have been formed by high‐dose (2×1016 cm−2) As implants. Experimental observations of As distributions and carrier concentrations are successfully simulated by a computer program which accounts for both the concentration dependent diffusion and As clustering effects. Reduction of electrical carriers in high‐dose As implanted Si during moderate temperature (∼800 ° C) heat treatments is readily explained by the kinetics of As clustering. Physical limitations on the conductivity which can be achieved by thermally annealed As implants in Si are also discussed.

Shallow junctions by high‐dose As implants in Si: experiments and modeling

Ellipsometry has been used to investigate damage in 1013‐1016/cm2 31P+‐implanted Si and crystallinity recovery by subsequent annealing. Implantation‐induced changes in optical constants, calculated from measured ellipsometric data, become prominent for implantation over the critical dose for amorphization. The refractive index increases with increasing implant dose, except when the implant dose exceeds 1015/cm2. The extinction coefficient increases monotonically with increasing implant dose and decreasing implant temperature. The dose dependence of the change in reflectivity shows a good agreement with the results by channeling effect analysis. For a sample implanted over the critical dose, optical constants and sheet resistances rapidly recover after annealing at around 500 °C, corresponding to epitaxial regrowths of implantation‐induced amorphous layers.

Characterization of 31P+‐implanted Si layers by ellipsometry

A semiconductor memory cell of a single field effect transistor and a single capacitor is surrounded or delimited at its three sides in the plan view by grooves formed in a semiconductor substrate. The capacitor in each memory cell is formed on one side wall surface or both side wall surfaces of this groove. With such construction, an increase in a capacitance can be achieved and a degree of circuit integration can be enhanced in distinction from the case where a groove is provided within an active region, that is, within a plan region of a capacitor section.

Dynamic ram with capacitor groove surrounding switching transistor

Diffusion of Al into a polycrystalline Si layer chemically deposited at 640 °C was studied by capacitance‐voltage characteristics, sheet resistance, and electron microprobe measurements in the 180–550 °C temperature range. It has been found that diffusion of Al into polycrystalline Si takes place at temperatures as low as 300 °C, and that the polycrystalline Si becomes electrically conductive. The sheet resistance of polycrystalline Si decreases with increasing annealing temperature. Annealing at a higher temperature, however, induces migration and recrystallization of Si in Al, and the original polycrystalline‐Si layer loses its integrity.

Low‐temperature diffusion of Al into polycrystalline Si

Low‐frequency excess noise characteristics of ion‐implanted MOS transistors annealed above 1000 °C were investigated. Noise characteristics strongly depended on implant species, implant condition, and measurement conditions. In the case of implantation into opposite‐type conductivity substrates, such as 11B+‐implanted p‐channel or 31P+‐implanted n‐channel transistors, the equivalent input noise voltages measured at lower drain currents exhibited generation‐recombination (G‐R) noise caused by residual damage in the substrate. This noise component increased with increasing acceleration energy or implant dose. The G‐R noise decreased with increasing drain current. At higher drain currents the G‐R noise disappeared and the noise voltages of the implanted samples were somewhat smaller than that of the unimplanted samples. On the contrary, in the case of implantation into the same‐type conductivity substrate, such as 31P+‐implanted p‐channel or 11B+‐implanted n‐channel transistors, no G‐R noise component was ob...

Noise Characteristics of Ion-Implanted Mos Transistors

11B+ ions of 1011−1012/cm2 were implanted through gate oxides of 800–2000 A into the channel regions of p‐channel MOS transistors. For 50‐keV implantation, the dose dependence of threshold voltage could be explained by Swanson and Meindl's theory. In the case of implantation above 100 keV, slight deviation of the threshold voltage from the theoretical values was observed. Corresponding to this, the gate‐oxide‐thickness dependence of the threshold voltage was slightly deviated from the theoretical values in the range of less than 1300 A. For more than 1500 A, the measured threshold voltages coincided with calculated values. The energy dependence of the dose limit for ``ability to turn on‐off'' showed good agreement with the curve calculated on the basis of Swanson and Meindl's theory within this experimental error. Source‐drain current in the saturation region was slightly increased with increasing dose at least up to 5 × 1011/cm2, presumably due to the carrier compensation (band bending) and increase of t...

Kunio Nakamura

Papers

Characterization of 31P+‐implanted Si layers by ellipsometry

Dynamic ram with capacitor groove surrounding switching transistor

Low‐temperature diffusion of Al into polycrystalline Si

Noise Characteristics of Ion-Implanted Mos Transistors

Electrical characteristics of ion‐implanted p‐channel MOS transistors