A survey is given of the recent literature on 1/ f noise. Proposals for mathematical models, for empirical relations and for physical models are discussed. The present situation is evaluated and some unsolved problems are indicated.

1/f noise

Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements. >

A physics-based MOSFET noise model for circuit simulators

A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

Publisher Summary This chapter discusses the flicker noise in electronic devices. The name “flicker noise” refers to the noise phenomena with a spectrum of the form AIβ/ƒɣ, here A is a constant, I is the current, ƒ is the frequency, and the exponents β and γ are also constants. The exponent β often has a value of about 2, though deviations are not uncommon. The theory of flicker noise as suppressed emission fluctuations cannot be valid, for in that case R, would be independent of d. Flicker partition noise indicates that the rate at which the current divides between the positive electrodes is randomly modulated by a I/ƒ-type process. The noise is due to fluctuations in the surface recombination velocity s and that there is direct experimental evidence in favor of it.

Flicker Noise in Electronic Devices

The backscattering method is employed to obtain microscopic information about solid‐solid reactions of Si with thin layers (500–2000 A) of both vacuum‐evaporated Au and sputtered Pt. A remarkable observation is the migration of Si atoms into Au and Pt at relatively low temperatures (150 and 350 °C, respectively). Migration of Si in Pt induces first the formation of Pt2Si‐like compounds and then PtSi. In the Au–Si system, on the other hand, Si moves through and accumulates on the Au surface in the form of SiO2 under an oxidizing heat‐treatment atmosphere.

Low‐temperature migration of silicon in thin layers of gold and platinum

Disclosed is a method of producing a semiconductor device in which a p-n junction and an ohmic contact with the semiconductor substrate are simultaneously formed. A layer of a metal containing an impurity of one conductivity type is deposited on a surface of a semiconductor body of the opposite conductivity type. The metal layer is then subjected to heat treatment, thereby to cause the impurity to diffuse into the semiconductor body to form the p-n junction. At the same time, a compound is formed of the metal and the semiconductor which serves as an ohmic contact with the semiconductor body at the region in which the impurity is diffused.

Method of making an ohmic contact with a semiconductor substrate

Ellipsometry has been used to investigate damage in 1013‐1016/cm2 31P+‐implanted Si and crystallinity recovery by subsequent annealing. Implantation‐induced changes in optical constants, calculated from measured ellipsometric data, become prominent for implantation over the critical dose for amorphization. The refractive index increases with increasing implant dose, except when the implant dose exceeds 1015/cm2. The extinction coefficient increases monotonically with increasing implant dose and decreasing implant temperature. The dose dependence of the change in reflectivity shows a good agreement with the results by channeling effect analysis. For a sample implanted over the critical dose, optical constants and sheet resistances rapidly recover after annealing at around 500 °C, corresponding to epitaxial regrowths of implantation‐induced amorphous layers.

Characterization of 31P+‐implanted Si layers by ellipsometry

Diffusion of Al into a polycrystalline Si layer chemically deposited at 640 °C was studied by capacitance‐voltage characteristics, sheet resistance, and electron microprobe measurements in the 180–550 °C temperature range. It has been found that diffusion of Al into polycrystalline Si takes place at temperatures as low as 300 °C, and that the polycrystalline Si becomes electrically conductive. The sheet resistance of polycrystalline Si decreases with increasing annealing temperature. Annealing at a higher temperature, however, induces migration and recrystallization of Si in Al, and the original polycrystalline‐Si layer loses its integrity.

Low‐temperature diffusion of Al into polycrystalline Si

Single‐step and double‐step annealing behavior of highly P+‐ion‐implanted layers was investigated by means of four‐point probe measurements, x‐ray double‐crystal spectrometry, and electron diffraction patterns. The x‐ray double‐crystal spectrometry data indicated that, in the case of single‐step annealing, the layer implanted with doses lower than 3×1015/cm2 ions was recovered with the increase of annealing temperature, while the sample implanted with doses of 1×1016/cm2 ions showed the opposite behavior. That is, the latter sample showed a very bad recrystallized layer with polycrystalline regions when it was annealed at temperatures higher than 1000 °C. However, in the case of double‐step annealing, the higher‐temperature annealing process, conducted after long 560 °C annealing, made it possible to obtain a good recrystallized layer, compared with the single‐step annealing case. These results were confirmed by electron diffraction patterns.

Annealing characteristics of highly P+‐ion‐implanted silicon crystal—two‐step anneal

Back-gate-bias V BG dependence of threshold voltage V T and gate-bias V G dependence of “gain” term β (and effective mobility μ eff ) of 50-keV-boron-implanted n -channel MOS transistors are described as functions of implant dose. In low field region, e.g. forward-biased V BG , the slopes of √[−( φ sub + V BG )] vs V T characteristics depend on the implant dose, while under high reverse bias, the slopes are constant and determined by the unimplanted substrate impurity concentration. Corresponding to this, the V G vs β ( μ eff ) characteristics indicate strong dose dependence and reduction of β ( μ eff ) in low field, while in high field the reduction of β ( μ eff ) is observed but not so significant. The effect is clear in the case of a deeply implanted layer or in case of a large ratio of effective channel length to width, as predicted by transistor equations.

Mototaka Kamoshida

Papers

Method of making an ohmic contact with a semiconductor substrate

Characterization of 31P+‐implanted Si layers by ellipsometry

Low‐temperature diffusion of Al into polycrystalline Si

Annealing characteristics of highly P+‐ion‐implanted silicon crystal—two‐step anneal

Electrical characteristics of boron-implanted n-channel MOS transistors