Kuo-Ning Chiang

TL;DR: In this paper, the authors developed solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages, and three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bumps geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results.

TL;DR: In this paper, the effect of die/substrate-side pad size and underfill size on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing.

TL;DR: In this article, a three-dimensional dual bumps simulation model was designed to demonstrate how current crowding can enhance the local atomic flux along the electron flow path, and the finding of void formation occurred at the entrance points to the cathode sides and the enhancement of the growth and clustering of the intermetallic compound at the outgoing points of the anode sides along the path were verified experimentally.

TL;DR: In this article, a finite element method (FEM) is adopted for sensor performance evaluation, packaging-induced signal variation, and thermal/packaging effects will be examined in this research.

TL;DR: In this article, a physics-based analytical model is proposed in order to predict the temperature profile during metal additive manufacturing (AM) processes, by considering the effects of temperature history in each layer, temperature-sensitivity of material properties and latent heat.