Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Bump-on-trace interconnect

The fabrication and characterization of a thermoelectric energy harvester using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technology were presented. The thermoelectric energy harvester is composed of eight circular energy harvesting cells, and each cell consists of 25 thermocouples in series. The thermocouples are made of p-type and n-type polysilicons. The output power of the energy harvester relies on the number of the thermocouples. In order to enhance the output power, the energy harvester increases the thermocouple number per area. The energy harvester requires a post-CMOS process to etch the sacrificial silicon dioxide layer and the silicon substrate to release the suspended structures of hot part. The experimental results show that the energy harvester has an output voltage per area of 0.178 mV·mm−2·K−1 and a power factor of 1.47 × 10−3 pW·mm−2·K−2.

Manufacturing and Characterization of a Thermoelectric Energy Harvester Using the CMOS-MEMS Technology

A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

Conical-shaped or tier-shaped pillar connections

A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

Substrate Interconnections having Different Sizes

This paper relates to the method of formation and structure of pillar bump with shape and dimension controllable, it specifically relates to a technique that uses polishing and planarization technique to let all pillar bumps have dimension and shape matching the design.

Structure and method of forming pillar bumps with controllable shape and size

In response to the essential role probe cards play in the semiconductor testing industry, a CMOS-MEMS force sensing devices capable of simultaneously monitoring the probe reacting force and electrical test signals is designed for probe cards. The probe reacting force can assist operators immediately to identify a broken, deformed, or worn-out probe and recognize that the measured electrical signals are erroneous. The debug time and cost of the IC test can therefore be effectively reduced. Array-type CMOS-MEMS force sensors are capable of monitoring the status of vertical probe cards on-line in the case of both die-level and wafer-level applications. The force sensor essentially is a Wheatstone-bridge-based piezoresistive force sensor with a small surface area and can be easily fabricated. It consists of a membrane composed of metal, silicon oxide, and a piezoresistive layer made of polycrystalline silicon. Moreover, as the conventional back-etch process can barely handle the increasingly smaller probe pitch, we use front etching to etch out a cavity under the membrane on the silicon substrate in order to deform the membrane during the post-process. For measuring the output signals of the sensors, on-chip circuits to scan and amplify the output signals of the sensors are integrated in the design process. Furthermore, a finite element method is adopted to analyze the structure of the sensors and to find the optimal piezoresistive sensor design. The TSMC 0.35 μm 2P4M process is used to fabricate the force sensors and the circuits. According to the measurement results, the designed sensor reports a sensitivity of 3.114 mV/N/V while a load-bearing force is 0.0294 N.

CMOS-MEMS piezoresistive force sensor with scanning signal process circuit for vertical probe card

In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the UIW (Uniformity in Wafer) could be sharply decreased from 6.37% after plating to 1.7% after polishing and even to 1.7% after reflow throughout the entire 4 inch wafer.

Kuo-Yu Lee

Papers

Structure and method of forming pillar bumps with controllable shape and size

CMOS-MEMS piezoresistive force sensor with scanning signal process circuit for vertical probe card

A novel high coplanarity lead free copper pillar bump fabrication process

An integrated electroless nickel plating process for fabrication of CMOS-MEMS probe chip

3D-flower-like porous neodymium molybdate nanostructure for trace level detection of organophosphorus pesticide in food samples.