Im Jahre 1977 wurde der „Data Encryption Algorithm“ (DEA) vom „National Bureau of Standards“ (NBS, später „National Institute of Standards and Technology“ – NIST) zum amerikanischen Verschlüsselungsstandard für Bundesbehörden erklärt [NBS_77]. 1981 folgte die Verabschiedung der DEA-Spezifikation als ANSI-Standard „DES“ [ANSI_81]. Die Empfehlung des DES als StandardVerschlüsselungsverfahren wurde auf fünf Jahre befristet und 1983, 1988 und 1993 um jeweils weitere fünf Jahre verlängert. Derzeit liegt eine Neufassung des NISTStandards vor [NIST_99], in dem der DES für weitere fünf Jahre übergangsweise zugelassen sein soll, aber die Verwendung von Triple-DES empfohlen wird: eine dreifache Anwendung des DES mit drei verschiedenen Schlüsseln (effektive Schlüssellänge: 168 bit) [NIST_99]. Der DES basiert auf einer von Horst Feistel bei IBM entwickelten Blockchiffre („Lucipher“) mit einer Schlüssellänge von 128 bit. Da die amerikanische „National Security Agency“ (NSA) dafür gesorgt hatte, daß der DES eine Schlüssellänge von lediglich 64 bit besitzt, von denen nur 56 bit relevant sind, und spezielle Substitutionsboxen (den „kryptographischen Kern“ des Verfahrens) erhielt, deren Konstruktionskriterien von der NSA nicht veröffentlicht wurden, war das Verfahren von Beginn an umstritten. Kritiker nahmen an, daß es eine geheime „Trapdoor“ in dem Verfahren gäbe, die der NSA eine OnlineEntschlüsselung auch ohne Kenntnis des Schlüssels erlauben würde. Zwar ließ sich dieser Verdacht nicht erhärten, aber sowohl die Zunahme von Rechenleistung als auch die Parallelisierung von Suchalgorithmen machen heute eine Schlüssellänge von 56 bit zum Sicherheitsrisiko. Zuletzt konnte 1998 mit einer von der „Electronic Frontier Foundation“ (EFF) entwickelten Spezialmaschine mit 1.800 parallel arbeitenden, eigens entwickelten Krypto-Prozessoren ein DES-Schlüssel in einer Rekordzeit von 2,5 Tagen gefunden werden. Um einen Nachfolger für den DES zu finden, kündigte das NIST am 2. Januar 1997 die Suche nach einem „Advanced Encryption Standard“ (AES) an. Ziel dieser Initiative ist, in enger Kooperation mit Forschung und Industrie ein symmetrisches Verschlüsselungsverfahren zu finden, das geeignet ist, bis weit ins 21. Jahrhundert hinein amerikanische Behördendaten wirkungsvoll zu verschlüsseln. Dazu wurde am 12. September 1997 ein offizieller „Call for Algorithm“ ausgeschrieben. An die vorzuschlagenden symmetrischen Verschlüsselungsalgorithmen wurden die folgenden Anforderungen gestellt: nicht-klassifiziert und veröffentlicht, weltweit lizenzfrei verfügbar, effizient implementierbar in Hardund Software, Blockchiffren mit einer Blocklänge von 128 bit sowie Schlüssellängen von 128, 192 und 256 bit unterstützt. Auf der ersten „AES Candidate Conference“ (AES1) veröffentlichte das NIST am 20. August 1998 eine Liste von 15 vorgeschlagenen Algorithmen und forderte die Fachöffentlichkeit zu deren Analyse auf. Die Ergebnisse wurden auf der zweiten „AES Candidate Conference“ (22.-23. März 1999 in Rom, AES2) vorgestellt und unter internationalen Kryptologen diskutiert. Die Kommentierungsphase endete am 15. April 1999. Auf der Basis der eingegangenen Kommentare und Analysen wählte das NIST fünf Kandidaten aus, die es am 9. August 1999 öffentlich bekanntmachte: MARS (IBM) RC6 (RSA Lab.) Rijndael (Daemen, Rijmen) Serpent (Anderson, Biham, Knudsen) Twofish (Schneier, Kelsey, Whiting, Wagner, Hall, Ferguson).

Advanced Encryption Standard (AES).

The ITU-T draft H.264 video coding standard has been designed enabling a new generation of digital video applications.While the basic coding framework of the standard is similar to that of currently popular video standard, H.264 includes many coding features not present in earlier standard. We firstly introduces the important features and key techniques in H.264. Then, we presents the performance of it. Study on the new generation ITU-T draft H.264 is of great importance in application field.

Overview of the H.264 / AVC Video Coding Standard

A symmetric block cipher employing a substitution-permutation duo is an effective technique for the provision of information security. For substitution, modern block ciphers use one or more substitution boxes (S-Boxes). Certain criteria and design principles are fulfilled and followed for the construction of a good S-Box. In this paper, an innovative technique to construct substitution-boxes using our cubic fractional transformation (CFT) is presented. The cryptographic strength of the proposed S-box is critically evaluated against the state of the art performance criteria of strong S-boxes, including bijection, nonlinearity, bit independence criterion, strict avalanche effect, and linear and differential approximation probabilities. The performance results of the proposed S-Box are compared with recently investigated S-Boxes to prove its cryptographic strength. The simulation and comparison analyses validate that the proposed S-Box construction method has adequate efficacy to generate efficient candidate S-Boxes for usage in block ciphers.

https://www.mdpi.com/1099-4300/21/3/245/pdf

A Novel Construction of Efficient Substitution-Boxes Using Cubic Fractional Transformation.

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Field Programmable Gate Array Applications—A Scientometric Review

A solution to get the problem off, have you found it? Really? What kind of solution do you resolve the problem? From what sources? Well, there are so many questions that we utter every day. No matter how you will get the solution, it will mean better. You can take the reference from some books. And the hardware implementation of finite field arithmetic is one book that we really recommend you to read, to get more solutions in solving this problem.

Hardware Implementation of Finite-field Arithmetic

In this paper, we propose an SAO hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC decoder. The proposed SAO hardware architecture introduces the design processing 8×8 CU to reduce the hardware area and uses internal registers to support 64×64 CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC 180nm library, the gate area is 30.7k and the maximum frequency is 250MHz.

http://ieeexplore.ieee.org/iel7/6653324/6664739/06664837.pdf

The hardware design of effective SAO for HEVC decoder

In this paper, we propose a highly efficient VLSI architecture for context-based adaptive variable-length coding (CAVLC) decoder. In multimedia data processing systems, the real-time processing requirement is the most critical problem and the only requirement that must be satisfied. Thus, an architecture which has a short processing time though a high throughput, can meet the requirement at low operating frequencies. Consequently, the architecture can have an advantage of low power consumption. We propose two methods to improve the throughput of CAVLC decoders. The first method eliminates the pipeline hazard in a pipelined architecture for CAVLC decoder. The second method expands the capacity of the barrel shifter. Experimental results show that the proposed architecture can improve throughput by about 45%. As a result, the proposed architecture greatly reduces the operating frequency for real-time processing, which is the key factor of reducing power consumption. The synthesis result shows that the design achieves the maximum operating frequency at 125 MHz, and the hardware cost is about 12.6 K under a 0.18 um CMOS process.

A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation

We have designed an SoC platform with a multi-channel bus architecture which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of OpenRISC 1200 processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. The proposed platform is implemented on Altera's EP2C70F672 FPGA device. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus.

SoC platform design with multi-channel bus architecture

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices

A compact, low power and low noise preamplifier for hearing aids is presented. The critical component at the heart of the preamplifier is an opamp, for which a modified current mirror serves for biasing it. The proposed opamp achieves a gain of 77dB, unit gain bandwidth of 182MHz and phase margin of 57°. A cascode structure has been used to realize a variable gain amplifier to maximize the output swing, and it achieves a gain range of 36dB. A new microphone, which mimics Ormia ochracea's auditory system, is used for design. It operates on a 1.3V zinc-air battery and within a 10kHz bandwidth, which is a sufficient audible frequency range for such application. At 100Hz the circuit exhibits a noise level of 331nV/sqrt(Hz). The circuit consumes a total power of 167μW The proposed circuit has been designed in a 0.13μm CMOS process and occupies an area of 1.026mm × 0.275mm.

Kwangki Ryoo

Papers

The hardware design of effective SAO for HEVC decoder

A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation

SoC platform design with multi-channel bus architecture

Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices

A low power and low noise preamplifier circuit for hearing aid devices