For the next generation of wearable health monitors, it is essential to develop stretchable and conformable sensors with robust electrical performance. These sensors should, in particular, provide a stable electrical output without being affected by external variables such as induced strain. Here, we report circuit design strategies that can improve the accuracy and robustness of a temperature sensor based on stretchable carbon nanotube transistors. Using static and dynamic differential readout approaches, our circuits suppress strain-dependent errors and achieve a measured inaccuracy of only ±1 oC within a uniaxial strain range of 0–60%. We address device variability by using a one-time, single-point calibration approach. In contrast with previous approaches, which infer temperature change through a normalized measurement at two temperatures, our prototype devices provide an absolute output without temperature cycling. This is essential for practical deployment because heating and cooling the sensor is prohibitively slow and costly during real-time operation and production testing. Using carbon nanotube transistors, stretchable temperature sensor circuits can be designed that suppress strain-dependent errors and achieve a measured inaccuracy of only ±1 °C within a uniaxial strain range of 0–60%

Stretchable temperature-sensing circuits with strain suppression based on carbon nanotube transistors

This paper describes a time-domain temperature sensor based on a successive approximation algorithm. Without using any bipolar transistor, a temperature sensor composed of a temperature-dependent delay line (TDDL) is utilized to generate a delay proportional to the measured temperature. A binary-weighted adjustable reference delay line (ARDL) is adopted with an effective delay varied by a SAR control logic to approximate the TDDL delay for output coding. For linearity enhancement, a curvature compensation between both delay lines is invented to achieve the best ever accuracy among inverter-delay-based smart temperature sensors. With two-point calibration, a -0.4°C ˜ +0.6°C inaccuracy (3σ) over a 0°C ˜ 90°C temperature operation range has been measured for 23 test chips. With 10 output bits, the proposed sensor achieves a resolution better than 0.1°C and a chip area of 0.6 mm2 in a TSMC 0.35-μm standard digital CMOS process. The sensor's average current consumption is 11.1 μA at a conversion rate of 2 samples/s.

A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of −0.4°C ∼ +0.6°C Over a 0°C to 90°C Range

We introduce a single-loop PLL that operates in a narrower-bandwidth, integer-N mode during phase lock and in a wider-bandwidth, fractional-N mode during transient This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shifts only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL, and as such, brings benefits in certain important PLL applications In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching A CMOS IC prototype attests to the validity of the proposed approach

/pdf/fast-lock-hybrid-pll-combining-fractional-n-and-integer-n-4i0zbec6zl.pdf

Fast-Lock Hybrid PLL Combining Fractional- $N$ and Integer- $N$ Modes of Differing Bandwidths

https://repository.tudelft.nl/islandora/object/uuid%3A1f575a3a-9427-4177-bd86-fce5ceb36b72/datastream/OBJ/download

Smart temperature sensors in standard CMOS

This paper presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratio of the frequency divider. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process, thereby reducing the settling time. To further enhance the locking speed, an auxiliary charge pump is employed to supply currents to the loop filter during the fast-locking mode to facilitate a rapid frequency acquisition. The proposed technique is incorporated in the design of a 5-GHz PLL. Fabricated in the TSMC 0.18-μm CMOS technology, the whole PLL dissipates 11 mA from a 1.8-V supply. The measured settling time is considerably improved over previous bandwidth-switching method. At 5.34 GHz, the phase noise measured at 1-MHz offset is -114.3 dBc/Hz, and the reference spurs at 10-MHz offset are lower than -70 dBc.

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

Today's microprocessors increasingly need on-chip temperature sensors for thermal and power management [1]. Since these sensors do not take part in the main computing activity but rather play the auxiliary, albeit important, role of temperature monitoring, their presence in terms of area, power, and design effort should be minimal, thus, all-digital sensors are desired. Temperature sensing based on temperature-dependent delays of inverters [2] could be suited for microprocessor applications, as it lends itself to digital implementation: by using a time-to-digital converter (TDC), an inverter delay can be compared to an absolute delay reference and converted to a digital temperature output [2] (Fig. 3.7.1). We report on an all-digital CMOS temperature sensor for microprocessor application, which also exploits temperature-dependent inverter delays within the TDC-based framework of Fig. 3.7.1. It, however, has two improvements over prior art of [2]. First, it removes the effect of process variation on inverter delays via calibration at one temperature point (instead of 2-point calibration of [2]), thus, reducing high volume production cost. Second, we use two fine-precision DLLs, one to synthesize a set of temperature-independent delay references in a closed loop, the other as a TDC to compare temperature-dependent inverter delays to the references. The use of DLLs simplifies sensor operation and yields a high measurement bandwidth (5kS/s) at 7b resolution, which could enable fast temperature tracking. This is in contrast to [2], where a counter-based cyclic TDC with an open-loop single delay-reference has a longer measurement time for a similar resolution.

Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring

We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 μJ/sample) and high bandwidth (5 kilo-samples/s), facilitating fast thermal monitoring. After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 μm fall within -4.0~4.0 °C in a temperature range of 0~100 °C, where the temperature chamber used has a control uncertainty of ±1.1 °C. Microprocessor thermal profiling can be a potential application.

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

The nonlinear transmission line is a structure where short-duration pulses called electrical solitons can be created and propagated. By combining, in a closed-loop topology, the nonlinear line and a special amplifier that provides not only gain but also mechanisms to tame inherently unruly soliton dynamics, we recently constructed the first electrical soliton oscillator that self-generates a stable, periodic train of electrical soliton pulses (Ricketts , IEEE Trans. MTT, 2006). This paper starts with a review of this recently introduced circuit concept, and then reports on new contributions, i.e., further experimental studies of the dynamics of the stable soliton oscillator and a CMOS prototype demonstrating the chip-scale operation of the stable soliton oscillator. Finally, we go to the opposite end of the spectrum and present a numerical study showing the possibilities that deliberate promotions of the unruly soliton dynamics in the closed-loop topology can produce chaotic signals.

/pdf/on-the-self-generation-of-electrical-soliton-pulses-1bx3w7h67b.pdf

On the Self-Generation of Electrical Soliton Pulses

A single-loop PLL that operates in a narrower-bandwidth, integer-N mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL. The frequency division mode switching facilitates a digital protocol to execute bandwidth switching, which increases the degree of design freedom for the bandwidth switching.

Kyoungho Woo

Papers

Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring

Fast-Lock Hybrid PLL Combining Fractional- $N$ and Integer- $N$ Modes of Differing Bandwidths

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

On the Self-Generation of Electrical Soliton Pulses

Hybrid Pll Combining Fractional-N & Integer-N Modes of Differing Bandwidths