Complex manufacturing machines, like ASML wafer scanners, consist of thousands of components like electronic boards, software, mechanical parts and optics. These components of multiple disciplines are assembled or integrated into modules. The modules are integrated into sub-systems forming the system, according to an integration plan. Components as well as modules, sub-systems, and systems, can be tested, diagnosed and ??xed, according to a test-diagnose- fix plan. An increase in the number of components results in an increase of the number of tasks in these plans. Moreover, the effort required to obtain a sequence that describes in which order the tasks should be executed also increases. The duration and the cost of a sequence depends on the quality of the system. In this project we introduce a method to analyze the duration and the cost of sequences of integration and test-diagnose-fix tasks. The method uses test-diagnose-fixed models to analyze the performance of sequences. The basic elements in such a model are: a) test, diagnose and fix tasks with their costs and durations, b) fault states, c) the coverage of test tasks on fault states, d) failure probabilities of fault states. These elements can be obtained for components, modules or sub-systems of multiple disciplines. Three case studies have been performed using this method. The outcome of the analysis indicates that choosing a di??erent test sequence can reduce the test duration by 30% to 70%. In addition, three techniques have been developed to improve integration and test-diagnose-fix sequences: ? To reduce the execution time of test-diagnose-fix sequences an algorithm has been developed to determine a new test task with an optimal coverage w.r.t. the fault states. The algorithm selects the new test task based on the maximum information gain. A test sequence, including the new test case, improves the test duration of the test-diagnose-fix task, because faults can be detected earlier. ? To reduce the execution time of test-diagnose-fix sequences an adapted hypergraph partitioning algorithm has been developed. The algorithm partitions a test-diagnose-??x task into smaller tasks which can be executed in parallel. The result of a case study is a reduction of the test duration by 30% with a concomitant increase of 30% in the test cost. ? The impact of the choice of the system architecture on the execution time and planning effort of integration and test-diagnose-fix sequences is investigated

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Integration and test strategies for complex manufacturing machines

On-board preventive maintenance: a design-oriented analytic study for long-life applications

Among the COTS applications in the X2000 architecture for deep-space missions, the use of commercial bus standards is the highest-payoff COTS application since a bus interface has a global impact and enabling effect on system cost and capability, respectively. While COTS bus standards enable significant cost reductions, it is a great challenge for us to deliver a highly-reliable long-term survivable system employing COTS standards that are not developed for mission-critical applications. The spirit of our solution to the problem is to exploit the pertinent standard features of a COTS product to circumvent its shortcomings, though these standard features may not be originally designed for highly reliable systems. In this paper we discuss our experiences and findings on the design and assessment of an IEEE 1394 compliant fault-tolerant bus architecture. We first derive and qualitatively analyze a "stack-tree topology" that not only complies with IEEE 1394 but also enables the implementation of a fault-tolerant bus architecture without node redundancy. We then present a quantitative evaluation that demonstrates significant reliability improvement from the COTS-based fault tolerance.

/pdf/cots-based-fault-tolerance-in-deep-space-qualitative-and-3ugqb5xr1o.pdf

COTS-based fault tolerance in deep space: Qualitative and quantitative analyses of a bus network architecture

In an attempt to increase the area utilization of multi-chip packages, manufacturers have started looking at 3D packaging. The 3D structures have either dies or chips stacked one above the other. These 3D structures have low thermal capabilities, and hence the thermal issues get aggravated during testing. In this paper, thermal aware test scheduling techniques for stacked structures is proposed. Care is taken to schedule the stacked partitions appropriately to prevent local heating and achieve uniform vertical temperature spread. Concurrent testing of dies is considered for reduced test time and existing test architecture is employed. The widely used global peak power model gives a pessimistic estimate of the power profile. A new partition scheme is proposed for the power profile based on power variations and true power. This scheme of power profile partitioning which is a trade-off between a cycle accurate model and global peak model offers both flexibility during scheduling and also reduces total false power. The power profile partitions are scheduled through algorithms based on heuristics. System model of the 3D stack is obtained from the linear RC-models after considering the various factors that affect the heat flow and die temperatures. Simulation results show that the proposed technique achieves uniform temperature spread across the 3D structure.

Thermal aware test scheduling for stacked multi-chip-modules

Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules

Advanced packaging technologies pose major testing challenges for complex designs. The authors present test strategies used in the space flight computer designed for NASA's Deep Space-1 mission.

Testing NASA's 3D-stack MCM space flight computer

Advanced packaging technologies such as 3D chip stacking, Multichip Modules (MCMs), and 3D stacks of MCMs provide an opportunity for significant reduction in system mass, volume and power. Unfortunately, it also poses some major testing challenges that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable assembly yields and meeting product quality requirements. Both these problems can be significantly reduced by adopting testing approaches which guarantee the integrity and performance of the 3D stack of MCMs. In this paper, we present test strategies for the 3D stack of MCMs used by the flight computer of the New Millenium Program (NMP) Deep Space-1 spacecraft, to be launched in July 1998. The proposed strategies are based on the IEEE 1149.1. Boundary Scan Standard architecture. Test chips are incorporated in some of the approaches for reliable test and diagnosis of a 3D MCM stack. Further, all the test strategies are compared and ranked with respect to test time, test hardware, number of test lines, and test reliability.

L. Alkalai

Papers

Testing NASA's 3D-stack MCM space flight computer

Test strategies for a 3-D stack multichip module space flight computer