CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

CMOS Data Converters for Communications

A time-interleaved multichannel analog-to-digital converter (ADC) achieves high sampling rates with the drawback of additional distortions caused by channel mismatches. In this paper, we consider the dependency of the signal-to-noise-and-distortion ratio (SINAD) on the combination of several different channel mismatch effects. By using either explicitly given mismatch parameters or given parameter distributions, we derive closed-form equations for calculating the explicit or the expected SINAD for an arbitrary number of channels. Furthermore, we extend the explicit SINAD by the impact of timing jitter. We clarify how channel mismatches interact and perform a worst case analysis of the explicit SINAD for individual mismatch errors. We also show that equations describing the expected SINAD of individual mismatch errors are special cases of our general formulation. We indicate how to use the expected SINAD for finding efficient optimization priorities and demonstrate the importance of worst case analyses.

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The impact of combined channel mismatch effects in time-interleaved ADCs

A/D and D/A conversion☆

Cascaded delta-sigma (MASH) modulators for higher order oversampled analog-to-digital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This first part of the paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents algorithms and architectures for digital correction of such analog imperfections, as well as gain and spectral distortion in the signal transfer function. Digital correction is implemented by linear finite-impulse response (FIR) filters, of which the coefficients are determined through adaptive off line or on-line calibration. Of particular interest is an on-line "blind" calibration technique, that uses no reference and operates directly on the digital output during conversion, with the only requirement on the unknown input signal that its spectrum be bandlimited. Behavioral simulations on dual-quantization oversampled converters demonstrate near-perfect adaptive correction and significant improvements in signal-to-quantization-noise performance over the uncalibrated case, using as few as 5 FIR coefficients. An alternative on line adaptation technique using test signal injection and experimental results from silicon are presented in the second part, in a companion paper.

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Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration

Conventional delta-sigma analog-to-digital converters (/spl Delta//spl Sigma/ADC's) are widely used in low-bandwidth applications such as high-fidelity audio processing because they offer high-precision conversion yet are amenable to implementation using fine-line VLSI processes optimized for digital circuitry. However, their oversampling requirement so far has prevented their widespread application to higher bandwidth applications such as video processing. This paper extends a recently developed delta-sigma ADC architecture called the pi-delta-sigma ADC (/spl Pi//spl Delta//spl Sigma/ADC) that consists of multiple /spl Delta//spl Sigma/ modulator channels operating in parallel without time-interleaving. The extension developed in this paper allows for oversampling to be combined with parallelism such that an M-channel system with an oversampling ratio of N can achieve a conversion performance close to that of a conventional /spl Delta//spl Sigma/ADC with an oversampling ratio of M/spl times/N. Thus, for a given conversion precision, the architecture offers relaxed oversampling relative to conventional /spl Delta//spl Sigma/ADCs in return for increased analog circuit area. Moreover, as will be shown, the /spl Pi//spl Delta//spl Sigma/ADC retains much of the robustness of conventional /spl Delta//spl Sigma/ADC's with respect to nonideal circuit behavior.

Oversampling parallel delta-sigma modulator A/D conversion

In this paper, the design procedure and practical issues regarding the realization of time-interleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary /spl Delta//spl Sigma/ topologies can be converted into corresponding time-interleaved structures. Practical issues such as finite opamp gain, mismatching, and DC offsets are addressed, analyzed, and practical solutions to overcome some of these problems are discussed. To verify the theoretical results, a discrete-component prototype of a second-order time-interleaved /spl Delta//spl Sigma/ analog/digital (A/D) converter has been implemented and the design details as well as experimental results are presented.

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L.B. Lim

Papers

Time-interleaved oversampling A/D converters: theory and practice