Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

CMOS Data Converters for Communications

This paper presents design algorithms for hybrid filter banks (HFBs) for high-speed, high-resolution conversion between analog and digital signals. The HFB is an unconventional class of filter bank that employs both analog and digital filters. When used in conjunction with an array of slower speed converters, the HFB improves the speed and resolution of the conversion compared with the standard time-interleaved array conversion technique. The analog and digital filters in the HFB must be designed so that they adequately isolate the channels and do not introduce reconstruction errors that limit the resolution of the system. To design continuous-time analog filters for HFBs, a discrete-time-to-continuous-time ("Z-to-S") transform is developed to convert a perfect reconstruction (PR) discrete-time filter bank into a near-PR HFB; a computationally efficient algorithm based on the fast Fourier transform (FFT) is developed to design the digital filters for HFBs. A two-channel HFB is designed with sixth-order continuous-time analog filters and length 64 FIR digital filters that yield -86 dB average aliasing error. To design discrete-time analog filters (e.g., switched-capacitors or charge-coupled devices) for HFBs, a lossless factorization of a PR discrete-time filter bank is used so that the reconstruction error is not affected by filter coefficient quantization. A gain normalization technique is developed to maximize the dynamic range in the finite-precision implementation. A four-channel HFB is designed with 9-bit (integer) filter coefficients. With internal precision limited to the equivalent of 15 bits, the maximum aliasing error is -70 dB, and with the equivalent of 20 bits internal precision, maximum aliasing is -100 dB. The 9-bit filter coefficients degrade the stopband attenuation (compared with unquantized coefficients) by less than 3 dB.

http://circuit.ucsd.edu/~nguyent/Nguyen/00668549.pdf

Design of hybrid filter banks for analog/digital conversion

A time-interleaved multichannel analog-to-digital converter (ADC) achieves high sampling rates with the drawback of additional distortions caused by channel mismatches. In this paper, we consider the dependency of the signal-to-noise-and-distortion ratio (SINAD) on the combination of several different channel mismatch effects. By using either explicitly given mismatch parameters or given parameter distributions, we derive closed-form equations for calculating the explicit or the expected SINAD for an arbitrary number of channels. Furthermore, we extend the explicit SINAD by the impact of timing jitter. We clarify how channel mismatches interact and perform a worst case analysis of the explicit SINAD for individual mismatch errors. We also show that equations describing the expected SINAD of individual mismatch errors are special cases of our general formulation. We indicate how to use the expected SINAD for finding efficient optimization priorities and demonstrate the importance of worst case analyses.

/pdf/the-impact-of-combined-channel-mismatch-effects-in-time-46oj642noi.pdf

The impact of combined channel mismatch effects in time-interleaved ADCs

A channelized digital ultrawideband (UWB) receiver that efficiently samples the UWB signal at a fraction of the chip frequency is proposed. The received signal is channelized in the frequency domain by employing a bank of mixers and low-pass filters. After sampling at a much reduced frequency, digital synthesis filters optimally estimate the transmitted signals. The signal-to-noise ratio (SNR) of the proposed receiver has been solved and compared against an ideal conventional receiver, which is defined as a receiver that samples at the signal Nyquist rate. When finite resolution analog-to-digital converters (ADC) are employed in the presence of a large narrowband interferer, the proposed receiver significantly outperforms the ideal conventional receiver. For example, the SNR of the proposed receiver is as much as 20 dB higher than the ideal conventional receiver when a 4-bit ADC is used in the presence of a 50 dB (relative to the noise floor) brickwall narrowband interferer with a bandwidth of 15% of the chip frequency.

/pdf/a-channelized-digital-ultrawideband-receiver-4i6qb3zhs1.pdf

A channelized digital ultrawideband receiver

In this paper, the design procedure and practical issues regarding the realization of time-interleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary /spl Delta//spl Sigma/ topologies can be converted into corresponding time-interleaved structures. Practical issues such as finite opamp gain, mismatching, and DC offsets are addressed, analyzed, and practical solutions to overcome some of these problems are discussed. To verify the theoretical results, a discrete-component prototype of a second-order time-interleaved /spl Delta//spl Sigma/ analog/digital (A/D) converter has been implemented and the design details as well as experimental results are presented.

/pdf/time-interleaved-oversampling-a-d-converters-theory-and-249k8qugxv.pdf

Time-interleaved oversampling A/D converters: theory and practice

A new architecture is proposed which exploits the time-interleaving concept to increase the oversampling ratio in delta-sigma modulators. It is shown that the effective oversampling ratio is increased by a factor M through the use of M interconnected modulators. Although a high speed sample-and-hold circuit is still required for an analogue-to-digital convertor, speed constraints are significantly reduced for the majority of analogue parts such as loop filters, A/D and D/A blocks.

Time-interleaved oversampling convertors

Recently, a new architecture was proposed which utilizes the concept of time-interleaving in oversampling converters. Using this architecture, one is theoretically able to achieve higher resolutions by using an array of interconnected modulators without increasing the oversampling ratio or order of the modulators. Alternatively, the same resolution can be maintained with wider bandwidth input signals. This paper presents the first experimental results on this new family of modulators. As well, the practical issue of component mismatch for these converters are studied and some suggestions are made to alleviate the effects of this problem. >

Mismatch effects in time-interleaved oversampling converters

In this paper, a new framework for the analysis of /spl Delta//spl Sigma/ modulators with stochastic inputs is proposed. The framework is based on assuming that the input to the one-hit quantizer is a Gaussian random process with zero mean and is thus able to interrelate the autocorrelation and cross-correlation of different signals of the modulator. Two main equations describing the behavior of two different /spl Delta//spl Sigma/ topologies are derived. These two equations are generally nonlinear and can be of arbitrary order, hence approximations are used to study some interesting cases. First, the nonlinear equations are linearized and solved analytically for first-order modulator with white inputs and numerically for colored inputs both with and without dithering. Also, a numerical iterative approach is used for second and fourth order modulators with white and colored inputs. In these cases, the variance of the one-bit quantizer input is found as a function of modulator input power. Next, the variance of the one-bit quantizer input is calculated when large amplitude oscillations are present assuming a large amplitude limit cycle to have a sinusoidal autocorrelation. Finally, an attempt is made to estimate the modulator's critical input power level beyond which these large amplitude limit cycles start. >

Analysis of /spl Delta//spl Sigma/ modulators with zero mean stochastic inputs

Comparator hysteresis of a 1-bit quantizer in /spl Delta/-/spl Sigma/ interpolative modulators is considered. A theoretical framework based on the describing function method is derived which enables estimation of the maximum and the minimum level at the input of the comparator, as well as the period of limit cycles with respect to the input. The results are in good agreement with simulation results, showing that hysteresis has a twofold worsening effect, i.e., increasing noise power and shifting the noise spectrum toward the signal band. >

R. Khoini-Poorfard

Papers

Time-interleaved oversampling A/D converters: theory and practice

Time-interleaved oversampling convertors

Mismatch effects in time-interleaved oversampling converters

Analysis of /spl Delta//spl Sigma/ modulators with zero mean stochastic inputs

On the effect of comparator hysteresis in interpolative /spl Delta//spl Sigma/ modulators