Showing papers in "IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing in 1997"

Design considerations for direct-conversion receivers

Abstract: This paper describes the issues and tradeoffs in the design and monolithic implementation of direct-conversion receivers and proposes circuit techniques that can alleviate the drawbacks of this architecture. Following a brief study of heterodyne and image-reject topologies, the direct-conversion architecture is introduced and effects such as dc offset, I/Q mismatch, even-order distortion, flicker noise, and oscillator leakage are analyzed. Related design techniques for amplification and mixing, quadrature phase calibration, and baseband processing are also described.

Spectral shaping of circuit errors in digital-to-analog converters

Abstract: Recently, various multibit noise-shaping digital-to-analog converters (DACs) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DACs have the potential to significantly increase the present precision limits of /spl Delta//spl Sigma/ data converters by eliminating the need for one-bit quantization in delta-sigma modulators. This paper extends the practicality of the noise-shaping DAC approach by presenting a general noise-shaping DAC architecture along with two special-case configurations that achieve first- and second-order noise-shaping, respectively. The second-order DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noise-the errors introduced by the analog circuitry-are not known to the noise-shaping algorithm.

Externally linear, time-invariant systems and their application to companding signal processors

Abstract: This paper considers externally linear, time-invariant systems which can be internally nonlinear and/or time-varying. Several examples of the synthesis of such systems are presented, and it is argued that they offer advantages in comparison to internally linear, time-invariant systems. In particular, their use in signal processing is considered, and it is shown that they can be designed to reduce the undesirable effects of overloading and noise corruption through the use of companding. It is shown that a variety of previously proposed schemes for this purpose are all related. Several practical problems are discussed, as are performance criteria and types of measurements needed for the evaluation of the systems discussed.

Pass-transistor adiabatic logic using single power-clock supply

Abstract: We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 /spl mu/ CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 /spl mu/ CMOS technology has been experimentally verified.

Analog-to-digital conversion via duty-cycle modulation

Abstract: An exchange of the amplitude axis for the time axis offers a possibility of overcoming resolution problems in analog-to-digital conversion in low-voltage CMOS circuits and/or of circumventing special resistor options in silicided processes. This exchange can be effected via some form of duty-cycle modulation. For its implementation a circuit configuration is described, consisting of an asynchronous sigma-delta modulator, followed by a phase-synchronized tapped ring oscillator which produces a poly-phase signal for sampling the asynchronous signal at a relatively low frequency. A detailed analysis is presented which accurately predicts the properties of the conversion scheme with respect to aliasing, quantization noise and nonlinear distortion. The results are illustrated with simulations of a design example.

Adaptive filters employing partial updates

Abstract: In some adaptive filtering applications, the least-mean-square (LBIS) algorithm may be too computationally- and memory-intensive to implement. In this paper, we analyze two adaptive algorithms that update only a portion of the coefficients of the adaptive filter per iteration. These algorithms use decimated versions of the error and regressor signals, respectively. Simulations verify the accuracy of the analyzes, and the robustness of the algorithms is also explored.

Background digital calibration techniques for pipelined ADCs

Abstract: A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDACs) commonly used in multistep or pipelined ADCs. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multistep or pipelined ADCs. The proposed method improves the performance of the inherently fast ADCs by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, of amp DC gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within two-thirds of the Nyquist bandwidth is recovered with 16-b accuracy using a forty-fourth order polynomial interpolation, behaving essentially as an FIR filter,.

Time-interleaved oversampling A/D converters: theory and practice

Abstract: In this paper, the design procedure and practical issues regarding the realization of time-interleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary /spl Delta//spl Sigma/ topologies can be converted into corresponding time-interleaved structures. Practical issues such as finite opamp gain, mismatching, and DC offsets are addressed, analyzed, and practical solutions to overcome some of these problems are discussed. To verify the theoretical results, a discrete-component prototype of a second-order time-interleaved /spl Delta//spl Sigma/ analog/digital (A/D) converter has been implemented and the design details as well as experimental results are presented.

Linear circuit fault diagnosis using neuromorphic analyzers

Abstract: This paper presents a method of analog fault diagnosis using neural networks. The primary focus of the paper is to provide robust diagnosis using a simple mechanism for automatic test pattern generation while reducing test time. A new diagnosis framework consisting of a white noise generator and an artificial neural network for response analysis and classification is proposed. This approach moves the diagnosis of analog circuits closer to the goal of built-in test. Networks of reasonable dimension are shown to be capable of robust diagnosis of analog circuits including effects due to tolerances.

Pulse-based analog VLSI velocity sensors

Abstract: We present two algorithms for estimating the velocity of a visual stimulus and their implementations with analog circuits using CMOS VLSI technology. Both are instances of so-called token methods, where velocity is computed by identifying particular features in the image at different locations; in our algorithms, these features are abrupt temporal changes in image irradiance. Our circuits integrate photoreceptors and associated electronics for computing motion onto a single chip and unambiguously extract bidirectional velocity for stimuli of high and intermediate contrasts over considerable irradiance and velocity ranges. At low contrasts, the output signal for a given velocity tends to decrease gracefully with contrast, while direction-selectivity is maintained. The individual motion-sensing cells are compact and highly suitable for use in dense 1-D or 2-D imaging arrays.

Algorithms for low power and high speed FIR filter realization using differential coefficients

Abstract: Most realizations of FIR filters use the coefficients directly to compute the convolution with the input data. We present a set of new algorithms for low power and high-speed realization of FIR filters. The algorithms use various orders of differences between coefficients for computing the convolution. Also the results of computations are stored and reused, thus requiring more storage and storage accesses. These techniques result in a reduction in the net computations necessary per convolution as compared to directly using the coefficients. It is shown analytically that this computational reduction at the cost of more storage can result in a lower net computational energy dissipated and an enhanced speed. These algorithms are applied to an example FIR filter to quantify the energy savings and speedup.

Generation of current conveyor-based all-pass filters from op amp-based circuits

Abstract: It is shown that two of the recently reported voltage mode and current mode current conveyor-based all-pass circuits can be generated from the well known single input op amp all-pass configuration. It is also found that two other voltage mode current conveyor-based all-pass circuits are related directly to the differential input op amp all-pass structure. Several new grounded capacitor all-pass circuits are introduced. A new universal biquad circuit which realizes complex poles and employs a single current conveyor is also given. PSpice simulation results are included.

Multifunction biquadratic filters using current conveyors

Abstract: Some novel multifunction biquadratic filters with voltage gain, each of which employs four current conveyors, two grounded capacitors, and three-five resistors, are presented. Each proposed circuit offers the following advantageous features: realization of different biquadratic filter signals from the same configuration, no requirements for component matching conditions, employment of only two grounded capacitors which are ideal for integration, orthogonal control of /spl omega//sub 0/ and Q and low sensitivities.

Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends

Abstract: Integrated circuit (IC) testing for quality assurance is approaching 50% of the manufacturing costs for some complex mixed-signal ICs. For many years the market growth and technology advancements in digital ICs were driving the developments in testing. The increasing trend to integrate information acquisition and digital processing on the same chip has spawned increasing attention to the test needs of mixed-signal ICs. The recent advances in wireless communications indicate a trend toward the integration of the RF and baseband mixed signal technologies. In this paper we examine the developments in IC testing from the historic, current status and future view points. In separate sections we address the testing developments for digital, mixed signal and RF ICs. With these reviews as context, we relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.

Design and implementation of a tunable 40 MHz-70 MHz Gm-C bandpass /spl Delta//spl Sigma/ modulator

Abstract: The discrete-time /spl Delta//spl Sigma/ modulator is transformed to the continuous-time /spl Delta//spl Sigma/ modulator. For either nonreturn to-zero or return to-zero feedback, the loop transfer functions of the continuous-time and discrete-time modulators can be made exactly equivalent. Hence, a stable discrete-time /spl Delta//spl Sigma/ modulator is mapped to a stable continuous-time /spl Delta//spl Sigma/ modulator having the same SNR. The anti-alias (image rejection) properties of the continuous-time modulator are described. Experimental results for a tunable 40 MHz-70 MHz continuous-time Gm-C modulator are shown to verify the theory. A master-slave tuning scheme is developed to tune the Gm-C /spl Delta//spl Sigma/ loop filter.

Design of recursive 1-D variable filters with guaranteed stability

Abstract: The digital filters with adjustable frequency-domain characteristics are called variable filters. Variable filters are used in many signal processing fields, but the recursive variable filters are extremely difficult to design due to the stability problem. This paper proposes a new method for designing recursive one-dimensional (1-D) variable filters whose stability is guaranteed. The method finds the coefficients of the transfer function of a variable digital filter as the multidimensional (M-D) polynomials of a few variables. The variables specify different frequency-domain characteristics, thus, we call the variables the spectral parameters. In applying the resulting variable filters, substituting different values of the spectral parameters into the M-D polynomials will obtain different filter coefficients and, thus, obtain different frequency-domain characteristics. To guarantee the stability, we first perform coefficient substitutions on the denominator coefficients such that they satisfy the stability conditions. Then both denominator and numerator coefficients are determined as M-D polynomials. In determining the M-D polynomials, we also propose an efficient least-squares approximation method that requires only solving simultaneous linear equations. Two examples are given to show the effectiveness of the proposed variable filter design technique.

Individual flip-flops with gated clocks for low power datapaths

Abstract: Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved.

Designing fuzzy logic systems

Abstract: We present a formulation of a fuzzy logic system (FLS) that can be used to construct nonparametric models of nonlinear processes, given only input-output data. In order to effectively construct such models, we discuss several design methods with different properties and features. We compare and illustrate systems designed with each one of the methods, using an example on the predictive modeling of a nonlinear dynamic (chaotic) system.

A linear fully balanced CMOS OTA for VHF filtering applications

Abstract: A linear, fully balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with large dc gain and wide bandwidth is described. The approach uses a two-differential-pair transconductor with a cross-coupled input stage together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated, dc gain enhancement is obtained without bandwidth limitation. SPICE simulations show that total harmonic distortion at 1.42 V/sub p-p/ is less than 1% with dynamic range equal to 66 dB at a power consumption of 2.7 mW from a single 5-V supply. As an example, the OTA is used to design a third-order elliptic lowpass filter in the very-high-frequency range, simulated in a standard 2 /spl mu/m CMOS process (MOSIS). The cutoff frequency of the filter is tunable in the range of 12-50 MHz.

IIR multiple notch filter design based on allpass filter

Abstract: A new technique for IIR multiple notch filter design is proposed. The specification of notch filter is first transformed into that of allpass filter. Then, we develop an effective approach to design this desired allpass filter. The realization of proposed notch filter is equivalent to the realization of an allpass filter. Due to the mirror-image symmetry relation between the numerator and denominator polynomials of allpass filter, the notch filter can be realized by a computationally efficient lattice structure with very low sensitivity. Moreover, some examples are presented to examine the effectiveness of proposed method.

A high-frequency integrable bandpass filter configuration

Abstract: Inductorless bandpass filters have in the past been realized using all-pass circuits based on op amps. This work replaces the op amps with integrable fixed gain amplifiers to create the bandpass filter. Values of Q exceeding 100 with resonant frequencies approaching 50 MHz can be achieved with an integrated circuit implementation. A method to reduce the sensitivity of Q with respect to temperature is reported.

Low power current-mode second-order bandpass IF filter

Abstract: A controlled active inductance implemented from two current-controlled conveyors in conjunction with one capacitor is introduced. Calculation, taking all the parasitics of the conveyors into account, shows that with this design the phase deviation from ideal is pushed up to very high frequency. A second order bandpass filter operating in current-mode has been implemented from this controlled inductance. This filter exhibits two bandpass outputs. One has unity gain and the other, which can be used for Q-tuning purpose, has a magnitude-gain at f/sub 0/ directly proportional to the Q-factor. An integrated circuit prototype of an IF receiver stage for the GSM cellular telephone has been designed from two cascaded identical second-order bandpass cells above. This circuit, which is intended to replace a surface acoustic wave (SAW) filter, was centered at 85 MHz. Simulation and measurement results are given for this prototype. They show interesting performances in conjunction with very low power consumption: less than 38 mW for the entire IF stage under /spl plusmn/2.5 V supply.

VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/)

Abstract: A modified parallel-in-parallel-out linear-systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). On the basis of the linear-systolic power-sum circuits, a VLSI architecture for exponentiation in GF(2/sup m/) is developed. Furthermore, two modified architectures that can be used to compute inverses and divisions over GF(2/sup m/) are proposed. All the architectures are constructed from m-1 linear-systolic power-sum circuits. It should be noted that the presented exponentiator, inverter, and divider are the only such circuits having a throughput of 100%. The latency of the presented pipeline exponentiator, inverter, and divider is m(m-1) clock cycles. The cycle time (i.e., clock period) of the presented architectures is only two logic gate delays plus a short routing delay. For moderate values of m, say m/spl les/10, the circuit complexity of the presented circuits is realizable using presently available VLSI technology. The computation time of near two gate delays and 100% throughput enables the greatest computation speed in finite field arithmetic.

VLSI architectures for lattice structure based orthonormal discrete wavelet transforms

Abstract: We present efficient single-rate architectures for the one-dimensional orthonormal discrete wavelet transform (DWT). In the paper we make two contributions. First, we show that architectures that are based on the quadrature mirror filter (QMF) lattice structure require approximately half the number of multipliers and adders than corresponding direct-form structures. Second, we present techniques for mapping the 1-D orthonormal DWT to folded and digit-serial architectures which are based on the QMF lattice structure. For folded architectures, we discuss two techniques for mapping the QMF lattice structure to hardware. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The proposed folded and digit-serial QMF lattice structures are attractive choices for implementations of the orthonormal DWT which require low area and low power dissipation.

A mathematical basis for power-reduction in digital VLSI systems

Abstract: Presented in this paper is a mathematical basis for power-reduction in VLSI systems. This basis is employed to: (1) derive lower bounds on the power dissipation in digital systems; and (2) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/s. Architectures implementing a given algorithm are equivalent to communication networks each with a certain capacity C (also in bits/s). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. By including various implementation constraints, increasingly realistic lower bounds are calculated. The usefulness of the proposed theory is demonstrated via numerical calculations of lower bounds on power dissipation for simple static CMOS circuits. Furthermore, a common basis for some of the known power-reduction techniques such as parallel processing, pipelining and adiabatic logic is also provided.

An architecture for the realization of a system for time-frequency signal analysis

Abstract: An architecture of the system for time-frequency signal analysis is presented. This system is based on the S-method, whose special cases are two the most important distributions: the spectrogram and the Wigner distribution. Systems with constant and signal-dependent window widths are presented.

Design of two-dimensional FIR digital filters by a two-dimensional WLS technique

Abstract: For two-dimensional (2-D) FIR filter design, the conventional weighted least squares (WLS) technique rearranges the filter parameters of 2-D form into their corresponding one-dimensional (1-D) form, thus resulting in expensive computation. This paper presents a new computationally efficient WLS technique for the design of 2-D FIR filters. We introduce an updating desired frequency response which implicitly includes the weighting function such that the sum of weighted square errors to be minimized can be represented in a 2-D matrix form. This makes it possible to keep all filter parameters in their natural 2-D form, thereby reducing the computational complexity from O(N/sup G/) to O(N/sup 3/). It is confirmed through design examples that the new technique is computationally very efficient and leads to nearly optimal approximations. This technique is suitable for the design of 2-D real zero-phase FIR filters with quadrantal symmetric or antisymmetric frequency response and can also be applied to the design of 1-D FIR filters.

Efficient digital filtering architectures using pipelining/interleaving

Abstract: A pipelining/interleaving (PI) technique is developed for efficient digital filtering. By using a clock rate that is K times the data rate and with interleaved feedback of the output samples, a single expanded digital filter H(z/sup K/) can be made equivalent to a cascade of k identical filters H/sup k/(z) 1/spl les/k/spl les/K. The PI technique is used for designing Kalser-Hamming sharpened linear-phase FIR filters with very high performance. It can also be applied in efficient IIR filtering to alleviate the critical-loop limitation on system clock rates. Furthermore, the PI technique is applicable to designing efficient multirate signal processing systems.

A Q-enhanced active-RLC bandpass filter

Abstract: A fully differential high-Q bandpass filter that uses lossy integrated inductors is presented. The circuit is implemented in a 0.8 /spl mu/m BiCMOS technology and realizes a center frequency of 750 MHz with a Q-factor that is tunable from 10 to 490 while dissipating 80-100 mW from a single 5 V supply. Since the objective of the prototype was to explore the proposed Q-enhancement technique, the dynamic range is limited to 25 dB for Q=20.

Suppression of multiple narrow-band interference using real-time adaptive notch filters

Abstract: The process of detection of narrow-band interference to a broad-band signal in a noisy environment using adaptive filtering techniques attributable to Kwan and Martin (1989) is further refined by modifying the gradient-search algorithm to reduce hardware complexity. The Kwan and Martin algorithm implies a geometric increase in hardware as the number of interferers increases. The improved method admits to only an arithmetic increase to achieve the similar results. Thus Kwan and Martin filters designed to handle 3 to 10 notches require 12.5% to 124% more hardware than the new filters. Simulations of the new method show it to be robust, functioning well in a variety of practical signal processing applications.