The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness. >

Short-channel effect in fully depleted SOI MOSFETs

The era of low power microelectronics began with the invention of the transistor in the late 1940's and came of age with the invention of the integrated circuit in the late 1950's. Historically, the most demanding applications of low power microelectronics have been battery operated products such as wrist watches, hearing aids, implantable cardiac pacemakers, pocket calculators, pagers, cellular telephones and prospectively the hand-held multi-media terminal However, in the early 1990's low power microelectronics rapidly evolved from a substantial tributary to the mainstream of microelectronics. The principal reasons for this transformation were the increasing packing density of transistors and increasing clock frequencies of CMOS microchips pushing heat removal and power distribution to the forefront of the problems confronting the advance of microelectronics. The distinctive thesis of this discussion is that future opportunities for low power gigascale integration (GSI) will be governed by a hierarchy of theoretical and practical limits whose levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit, and (5) system. >

/pdf/low-power-microelectronics-retrospect-and-prospect-52qjazszpc.pdf

Low power microelectronics: retrospect and prospect

In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.

VLSI limitations from drain-induced barrier lowering

An accurate and convenient method to determine an effective MOSFET channel length is proposed. This method is based on a computer aided evaluation of an intrinsic MOSFET channel resistance without using special test devices. N-channel silicon-gate MOSFETs were fabricated, and the channel length and its range of device to device scatter were evaluated . To define an effective channel, a simple model of the source-drain (S-D) diffusion layer is proposed. This model shows that the expected transition layer resistance between the S-D diffusion layer and the inverted channel layer agrees with the experimental results. The accuracy of this method is also discussed. It is found to be better than 0.1 µm.

https://iopscience.iop.org/article/10.1143/JJAP.18.953/pdf

A New Method to Determine Effective MOSFET Channel Length

A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects. The expression is derived for zero drain voltage and is valid for short and long-channel lengths. The dependence of the threshold voltage on the source and drain diffusion depth, r j , and channel length, L , is explicitly given. In the limit, L / r j → ∞, the threshold voltage equation reduces to the familiar expression for the long-channel case. The theory is compared with the measured threshold voltages on IGFET's fabricated with 1·4, 3·8 and 7·4 μm channel lengths. The dependence of the threshold voltage under backgate bias voltages ranging from zero to breakdown agrees closely with the theory.

L.D. Yau

Papers

A simple theory to predict the threshold voltage of short-channel IGFET's