Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

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Principles of Asynchronous Circuit Design: A Systems Perspective

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-/spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.

An efficient charge recovery logic circuit

A 38-ns, 257-mW, 16*16-b CMOS multiplier with a supply voltage of 4 V is described A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 26 ns with 60 mW at 77 K >

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic

Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of CMOS technology optimized for high-frequency design. Complex circuit styles were used extensively to meet aggressive cycle time goals. CAD tools were developed internally to support these designs. This paper discusses some of the technologies that have enabled Alpha microprocessors to achieve high performance.

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High-performance microprocessor design

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

Cascode voltage switch logic: A differential CMOS logic family

A balanced charge-transfer sense amplifier for one-device cell memory arrays is presented. Charge-transfer techniques are used to preamplify the sense signal and to isolate the large bit/sense (B/S) line capacitance from the nodes of a dynamic latch. The high sensitivity of the sense-refresh amplifier is demonstrated in an experimental memory array with a B/S line to ell storage node capacitance ratio of 40 and a sense signal of about 61 mV. Performance limitations are also discussed.

High sensitivity charge-transfer sense amplifier

A double cross-coupled MOS charge-transfer sense amplifier for application to dynamic one-device cell memory arrays will be presented. Sensitivity is better than 1OmV.

L. Heller

Papers

Cascode voltage switch logic: A differential CMOS logic family

High sensitivity charge-transfer sense amplifier

Cross-coupled charge-transfer sense amplifier