Proceedings ArticleDOI
Cascode voltage switch logic: A differential CMOS logic family
L. Heller,W. Griffin,J. Davis,N. Thoma +3 more
- pp 16-17
TLDR
A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described.Abstract:
A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.read more
Citations
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Book
Principles of Asynchronous Circuit Design: A Systems Perspective
Jens Spars,Steve Furber +1 more
TL;DR: Industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.
Journal ArticleDOI
An efficient charge recovery logic circuit
Yong Moon,Deog-Kyoon Jeong +1 more
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Journal ArticleDOI
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic
Kazuo Yano,Toshiaki Yamanaka,Takashi Nishida,M. Saito,Katsuhiro Shimohigashi,Akihiro Shimizu +5 more
TL;DR: In this article, a complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path, which consists of complementary inputs/outputs, an nMOS pass transistor logic network, and CMOS output inverters, and is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality.
Journal ArticleDOI
High-performance microprocessor design
TL;DR: Three generations of Alpha microprocessors have been designed using a proven custom design methodology that facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths.
Patent
Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
Alistair D. Black,Kurt Chan +1 more
TL;DR: In this article, a switch, switched architecture and process for transferring data through an FCAL switch is disclosed, which uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch.
References
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Journal ArticleDOI
Optimization by Simulated Annealing
TL;DR: There is a deep and useful connection between statistical mechanics and multivariate or combinatorial optimization (finding the minimum of a given function depending on many parameters), and a detailed analogy with annealing in solids provides a framework for optimization of very large and complex systems.
Journal ArticleDOI
High-speed compact circuits with CMOS
TL;DR: A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.
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