Purpose – The purpose of this paper is to present the power noise characteristics of a multilayer printed circuit board (PCB) in which discrete capacitors have been embedded.Design/methodology/approach – Embedded technology has been implemented on a multilayer PCB to enhance the performance and functionality and to decrease the power noise. Decoupling capacitors were directly positioned on the inner power planes of a board, which resulted in low‐loop inductance through the minimized length of the interconnection from the chips to the PCB's power delivery network.Findings – A low‐noise PCB was successfully designed and fabricated using an embedding process for the discrete decoupling capacitors. It was demonstrated that such an approach offers lower interconnection inductance and quiet noise performance, including highly efficient propagation noise suppression at wideband frequencies.Research limitations/implications – Most conventional simulation techniques offer expectations for the signal characteristic...

Low‐power noise multilayer PCB with discrete decoupling capacitors inside

In this paper, we describe the design and implementation of the low noise interconnection (low power plane impedance) in multilayer boards using embedded discrete capacitor technology. To obtain the low noise solutions over a wide range of operating frequency, the overshoot resonances excited at some frequencies should be firstly analyzed. Some resonances make the signal and power integrity problems in the high speed digital boards. To solve these issues related with overshoot resonances, the equivalent circuit model for a PDN should be developed. It is well known that the transmission line matrix (TLM) model serves a proper design method for power delivery network (PDN) including the power/ground plane, via, capacitors, and so on. As using this TLM method, the power impedance and overshoot resonance for the designed PDN can be estimated. Therefore, the power impedance and some resonances on PDN can be easily approached and optimized for low noise interconnection design. The discrete capacitors are conventionally used to minimize the power impedance at any frequency band where the impedance of the decoupling capacitor is lower than that of the power/ground planes pair. However, the increase of equivalent series inductance (ESL) in the discrete capacitor degrades the low noise frequency bandwidth under the multilayer board environments. It is noted that the embedded discrete capacitor structure presented in this paper can be used to maintain the parasitic inductance of the decoupling capacitor as low as possible to decrease the overshoot of the resonance frequency. According to our experimental results, the resonance magnitude and power noise characteristic are from 15 ? to 1 ? and from -53 dBm to -64 dBm, respectively.

Low Power Noise Multilayer PCB with Discrete Decoupling Capacitors Inside

The embedded DRAM (eDRAM) is more and more used in system-on-chip (SOC). It is challenging to integrate the DRAM capacitor process into a logic process to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (/spl sim/30 fF) of this device induce problems of process monitoring and failure analysis. We propose a new test structure to measure the capacitance value of each DRAM cell capacitor in a DRAM array. This concept has been validated by simulation on a 0.18 /spl mu/m eDRAM technology.

https://hal.archives-ouvertes.fr/hal-00181649/document

L. Lopez

Papers

A New Embedded Measurement Structure for eDRAM Capacitor