The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for every new design. Analog-to-Digital Conversion discusses the different analog-to-digital conversion principles: sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation. Analog-to-Digital Conversion presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed while reducing the power level. A lot of background knowledge and practical tips complement the discussion of basic principles, which makes Analog-to-Digital Conversion also a reference for the experienced engineer.

Analog-to-Digital Conversion

This paper provides a comparison between two techniques for soft fault diagnosis in analog electronic circuits. Both techniques are based on the simulation before test approach: a "fault dictionary" is a priori generated by collecting, signatures of different fault conditions. Classifiers, trained by the examples contained in the fault dictionary, are then configured to classify the measured circuit responses. The suggested classifiers have similar structures. The first is based on a fuzzy system, obtained by processing fault dictionary data for automatic generation of IF-THEN rules, and the second classifier is based on a radial basis function neural network. The two classifiers are used to detect and isolate faults both at the subsystem and component levels. The experimental results point out that both classifiers provide low classification errors in the presence of noise and nonfaulty components tolerance effects. The fuzzy approach provides better results due to an efficient generation method for the IF-THEN rules that allows adding IF parts in the input space regions where ambiguity occurs.

Soft fault detection and isolation in analog circuits: some results and a comparison between a fuzzy approach and radial basis function networks

A new approach to an optimal analog test points selection is proposed. The described method uses ambiguity set concept and evolutionary computations to determine the optimal set of analog test points. After a brief introduction to analog testing and genetic algorithms, the proposed strategy is explained. The presented evolutionary approach is illustrated by a practical example of analog circuit and by a series of hypothetical circuits. The efficiency of the technique is compared with a method based on entropy index, and the obtained results are discussed

Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection

There are mainly two factors responsible for rapidly escalating production test costs of today's RF and high-speed analog circuits: 1) the high cost of high-speed and RF automatic test equipments and 2) long test times required by elaborate performance tests. In this paper, we propose a low-cost signature test methodology for accelerated production testing of analog and RF integrated circuits. As opposed to prior work, the key contribution of this paper is a new test generation algorithm that directly tracks the ability of input test waveforms to predict the test specification values from the observed test response, even in the presence of measurement noise. The response of the device-under-test (DUT) is used as a "signature" from which all of the performance specifications are predicted. The applied test stimulus is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. While existing low-cost test approaches have only been applied to low- and medium-frequency analog circuits, the proposed methodology extends low-cost signature testing to RF integrated circuits by incorporating modulation of a baseband test stimulus and subsequent demodulation of the obtained response to obtain the DUT signature. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester

Signature Testing of Analog and RF Circuits: Algorithms and Methodology

In this paper, we propose a unified approach to partitioning, floorplanning, and retiming for effective and efficient performance optimization. The integration enables the partitioner to exploit more realistic geometric delay model provided by the underlying floorplan. Simultaneous consideration of partitioning and retiming under the geometric delay model enables us to hide global interconnect latency effectively by repositioning FF along long wires. Under the proposed geometric embedding based performance driven partitioning problem, our GEO algorithm performs multi-level top-down partitioning while determining the location of the partitions. We adopt the concept of sequential arrival time [14] and develop sequential required time in our retiming based timing analysis engine. GEO performs cluster-move based iterative improvement on top of multi-level cluster hierarchy [4], where the gain function obtained from the timing analysis is based on the minimization of cutsize, wirelength, and sequential slack. In our comparison to (i) state-of-the-art partitioner hMetis [9] followed by retiming [11] and simulated annealing based slicing floorplanning [15], and (ii) state-of-the-art simultaneous partitioning with retiming HPM [7] followed by floorplanning [15], GEO obtains 35% and 23% better delay results while maintaining comparable cutsize, wirelength, and runtime results.

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Physical planning with retiming

Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

L.S. Milor

Papers

A tutorial introduction to research on analog and mixed-signal circuit testing