Structural Design and Pyroelectric Property of SnS/CdS Heterojunctions Contrived for Low-Temperature Visible Photodetectors

In this paper, we report the influence of thermal annealing on structural, electrical properties V2O5 thin films and their application of SBD’s. V2O5 thin films were prepared using glass substrate by sol gel spin coating technique. Films were annealed at different temperatures such as 300 °C, 400 °C and 500 °C. The prepared films were introduced as an interfacial layer between metal and semiconductor interface. V2O5 films exhibit single phase tetragonal structure and surface morphology interestingly, it was changed into nanorod-like structure at higher annealing temperature which was observed through field emission scanning electron microscopy. Atomic force microscopy reveals the surface roughness and the mentioned roughness is increasing due to the increase of annealing temperature. The elemental composition was confirmed by energy dispersive X-ray spectrum. From UV–Vis absorption spectroscopy results revealed that the band gap shows a decreasing trend on increasing the annealing temperature. Besides, we analyzed the influence of high quality vanadium pentoxide (V2O5) thin films prepared at different annealed temperatures and act as an interfacial layer between metal and semiconductor in the fabrication of Schottky diode. V2O5 films depicts high electrical conductivity (σdc) of 0.945 (S cm−1) with activation energy of 0.0747 eV (Ea) as a function of temperature. The MIS structured Cu/V2O5/n-Si based SBD’s diode performance was analyzed for different temperatures ranging from 30 to 150 °C. V2O5 thin-film act as an interfacial layer on Cu/V2O5/n-Si Schottky diode was successfully explained by the thermionic emission theory.

Impact of Annealing Temperature on Spin Coated V2O5 Thin Films as Interfacial Layer in Cu/V2O5/n-Si Structured Schottky Barrier Diodes

The performance of a 4H-SiC Schottky diode for thermal sensing in the wide temperature range from $T=85$ up to 443 K is presented. The linear dependence on temperature of the forward voltage drop, for different bias currents, is investigated through an analytical study of the temperature-dependent physical Schottky diode parameters. A high sensitivity of 1.18 mV/K was observed for a constant bias current of $I_{D}=80 \,\,\mu \text{A}$ . The device exhibits a good degree of linearity with a calculated root mean square error, with respect to the best-linear fitting model, lower than 2.7 mV. Moreover, the proposed sensor shows a good repeatability maintaining a stable output over more cycles of measurements, from (down to) 85 up to (from) 443 K, in a long period of time.

85–440 K Temperature Sensor Based on a 4H-SiC Schottky Diode

Influence of rare earth doping concentrations on the properties of spin coated V2O5 thin films and Cu/Nd-V2O5/n-Si Schottky barrier diodes

The anisotropic field effect mobilities of four prototypical semiconducting materials, that is, single crystals of pentacene, tetracene, picene, and rubrene, are evaluated by using the hopping model with time averaged rates obtained at the second-order cumulant (SOC) expansion of the time-dependent reduced density matrix. It is shown that the SOC approach allows for correcting the two known failures of the hopping mechanism: the highly overestimated mobilities provided by the Fermi golden rule and the incorrect temperature dependence predicted by the semiclassical Marcus’ approach.

Second-Order Cumulant Approach for the Evaluation of Anisotropic Hole Mobility in Organic Semiconductors

A new analytical description of the trapped charge distribution at the semiconductor–insulator interface of 4H-SiC vertical-DMOSFET has been derived as a function of the surface potential into the channel. The model allows one to accurately calculate the electrical characteristics of the device in both subthreshold and above-threshold operations, namely, when the channel works from weak accumulation to strong inversion. The accuracy of the model has been verified by comparisons with numerical simulations and with experimental measurements of a 1.7-kV commercial device.

Modeling of the SiO 2 /SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

The Bachet weight decomposition method is used to design a new 2D convolution-based filter, specifically aimed to image processing. The filter substitutes multipliers with simplified floating point adders to emulate standard 32 bit floating point multipliers, by using a set of pre-computed coefficients. A careful organization of the memory, together with the optimized distribution of the related hard macros in the FPGA fabric, allow the elaboration of the data in raster scan order, as those directly provided by an acquisition source, without the need of frame buffers or additional aligning circuitry. The proposed design achieves a state-of-the-art critical path delay of 4.7 ns on a Xilinx Virtex 7 FPGA.

FPGA optimization of convolution-based 2D filtering processor for image processing

A custom Human Activity Recognition system is presented based on the resource-constrained Hardware (HW) implementation of a new partially binarized Hybrid Neural Network. The system processes data in real-time from a single tri-axial accelerometer, and is able to classify between 5 different human activities with an accuracy of 97.5% when the Output Data Rate of the sensor is set to 25 Hz. The new Hybrid Neural Network (HNN) has binary weights (i.e. constrained to +1 or −1) but uses non-binarized activations for some layers. This, in conjunction with a custom pre-processing module, achieves much higher accuracy than Binarized Neural Network. During pre-processing, the measurements are made independent from the spatial orientation of the sensor by exploiting a reference frame transformation. A prototype has been realized in a Xilinx Artix 7 FPGA, and synthesis results have been obtained with TSMC CMOS 65 nm LP HVT and 90 nm standard cells. Best result shows a power consumption of $6.3~\mu \text{W}$ and an area occupation of 0.2 mm $^{\mathbf {2}}$ when real-time operations are set, enabling in this way, the possibility to integrate the entire HW accelerator in the auxiliary circuitry that normally equips inertial Micro Electro-Mechanical Systems (MEMS).

A Partially Binarized Hybrid Neural Network System for Low-Power and Resource Constrained Human Activity Recognition

In this paper, an energy efficient HW accelerator for AI edge-computing in Human Activity Recognition is proposed. The system processes samples from a tri-axial accelerometer and classifies the human activities by using a novel Hybrid Neural Network (HNN) topology, which has been designed to reduce the computational complexity of the system while preserving its accuracy. The HW design improves the characteristics of the HNN by means of an architecture that is aimed to reduce the allocated physical resources and the memory accesses. While accuracy measured on ad-hoc dataset is 97.5 %, measurements from synthesis with CMOS 65 nm standard cells report power consumption of 6.3 μW when the sensor output data rate is 25 Hz, normally used for HAR.

Low-Power HWAccelerator for AI Edge-Computing in Human Activity Recognition Systems

Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. Aiming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.

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Luigi Di Benedetto

Papers

Modeling of the SiO 2 /SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

FPGA optimization of convolution-based 2D filtering processor for image processing

A Partially Binarized Hybrid Neural Network System for Low-Power and Resource Constrained Human Activity Recognition

Low-Power HWAccelerator for AI Edge-Computing in Human Activity Recognition Systems

Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems