This paper reviews the current state of power supply technology platforms and highlights future trends and challenges toward realizing fully monolithic power converters. This paper presents a detailed survey of relevant power converter technologies, namely power supply in package and power supply on chip (PwrSoC). The performance of different power converter solutions reported in the literature is benchmarked against existing commercial products. This paper presents a detailed review of integrated magnetics technologies, primarily microinductors, a key component in realizing a monolithic power converter. A detailed review and comparison of different microinductor structures and the magnetic materials used as inductor cores is presented. The deposition techniques for integrating the magnetic materials in the microinductor structures are discussed. This paper proposes the use of two performance metrics or figures of merit in order to compare the dc and ac performance of individual microinductor structures. Finally, the authors discuss future trends, key challenges, and potential solutions in the realization of the “holy grail” of monolithically integrated power supplies (PwrSoC).

Review of Integrated Magnetics for Power Supply on Chip (PwrSoC)

On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range of output voltages compared to a 1/2 mode switched-capacitor converter. The test-chip prototype delivers up to 0.85 A load current while generating output voltages from 0.4 to 1.4 V from a 2.4 V input supply. It achieves 77% peak efficiency at power density of 0.1 W/mm2 and 63% efficiency at maximum power density of 0.3 W/mm2. The converter scales output voltage from 0.4 V to 1.4 V (or vice-versa) within 20 ns at a constant 450 mA load current. A shunt regulator reduces peak-to-peak voltage noise from 0.27 V to 0.19 V under pseudo-randomly fluctuating load currents. Using simulations across a wide range of design parameters, the paper compares conversion efficiencies of the 3-level, buck and switched-capacitor converters.

A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS

This paper surveys and discusses the state-of-the-art of integrated switched-capacitor and inductive power converters. After introducing applications that drive the need for integrated switching power converters, implementation issues to be addressed for integrated switched-capacitor and inductive converters are given, as well as design examples. At the end of this paper, a comprehensive set of integrated power converters are compared in terms of the main specifications and performance metrics, thereby allowing a categorization and providing application-oriented design guidelines.

Survey and Benchmark of Fully Integrated Switching Power Converters: Switched-Capacitor Versus Inductive Approach

In recent years, chip multiprocessor architectures have emerged to scale performance while staying within tight power constraints. This trend motivates per-core/block dynamic voltage and frequency scaling (DVFS) with fast voltage transition. Given the high cost and bulk of off-chip DC/DC converters to implement multiple on-chip power domains, there has been a surge of interest in on-chip converters. This paper presents the design and experimental results of a fully integrated 3-level DC/DC converter [1] that merges characteristics of both inductor-based buck [2–4] and switched-capacitor (SC) converters [5]. While off-chip buck converters show high conversion efficiency, their on-chip counterparts suffer from loss due to low quality inductors. With the help of flying capacitors, the 3-level converter requires smaller inductors than the buck converter, reducing loss and on-die area overhead. Compared to SC converters that need more complex structures to regulate higher than half the input voltage, 3-level converters can efficiently regulate the output voltage across a wide range of levels and load currents. Measured results from a 130nm CMOS test-chip prototype demonstrate nanosecond-scale voltage transition times and peak conversion efficiency of 77%.

A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation

This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed converter achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or voltage conversion range. The D-PLL is programmable over a wide range of parameters and can be synchronized to a clock reference to ensure proper frequency lock and switching operation outside undesirable power supply resonance bands. The stability and loop dynamics of the proposed converter is analyzed using an analog equivalent PLL behavioral model which describes the dc-dc converter as a voltage-controlled oscillator (VCO). We demonstrate a 90-240 MHz single phase converter with fast hysteretic control and output conversion range of 33%-80%. The converter achieves an efficiency of 80% at 180 MHz, a load response of 40 ns for a 120 mA current step and a peak-to-peak ripple less than 25 mV. The circuit was implemented in 130 nm digital CMOS process.

A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization

A fully integrated 0.18 mum DC-DC buck converter using a low-swing ldquostacked driverrdquo configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals.

A Fully Integrated 660 MHz Low-Swing Energy-Recycling DC–DC Converter

A 90nm buck converter is intended for complex multi-core ICs. Using the 3GHz system clock for switching reduces the area to 0.27mm2 and allows the output filter to be integrated. Efficiency is increased by recycling clock charge and delivering it to the load instead of ground. A dedicated 3GHz clock circuit driving 12pF consumes 39.9mW. In contrast, a combined clock and converter circuit consumes 56.2mW and delivers 25.7mW at the converter output. Regulation is achieved through PWM of the clock. The circuit converts 1.0V to between 0.5 to 0.7V at 40 to 100mA.

/pdf/a-3ghz-switching-dc-dc-converter-using-clock-tree-charge-33qa656rvc.pdf

A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660 MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18mum CMOS are included. The circuit converts 2.2V to 0.75~1.0V at ~55 mA.

/pdf/a-660mhz-zvs-dc-dc-converter-using-gate-driver-charge-39nay4ddxj.pdf

A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an Integrated Output Filter

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages.

Energy Recovery from High-Frequency Clocks Using DC-DC Converters

This paper advocates dasiareduce, reuse, recyclepsila as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18 mum CMOS, operates at 660 MHz, and converts 2.2 V to 0.75-1.0 V at ~50 mA.

/pdf/soc-energy-savings-reduce-reuse-recycle-a-case-study-using-a-57lwf65wgg.pdf

M. Alimadadi

Papers

A Fully Integrated 660 MHz Low-Swing Energy-Recycling DC–DC Converter

A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter

A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an Integrated Output Filter

Energy Recovery from High-Frequency Clocks Using DC-DC Converters

SoC energy savings = reduce+reuse+recycle: A case study using a 660MHz DC-DC converter with integrated output filter