This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

Millimeter wave (mmWave) communication has raised increasing attentions from both academia and industry due to its exceptional advantages. Compared with existing wireless communication techniques, such as WiFi and 4G, mmWave communications adopt much higher carrier frequencies and thus come with advantages including huge bandwidth, narrow beam, high transmission quality, and strong detection ability. These advantages can well address difficult situations caused by recent popular applications using wireless technologies. For example, mmWave communications can significantly alleviate the skyrocketing traffic demand of wireless communication from video streaming. Meanwhile, mmWave communications have several natural disadvantages, e.g., severe signal attenuation, easily blocked by obstacles, and small coverage, due to its short wavelengths. Hence, the major challenge is how to overcome its shortcomings while fully utilizing its advantages. In this paper, we present a taxonomy based on the layered model and give an extensive review on mmWave communications. Specially, we divide existing efforts into four categories that investigate: physical layer, medium access control (MAC) layer, network layer, and cross layer optimization, respectively. First, we present an overview of some technical details in physical layer. Second, we summarize available literature in MAC layer that pertains to protocols and scheduling schemes. Third, we make an in-depth survey of related research work in network layer, providing brain storming and methodology for enhancing the capacity and coverage of mmWave networks. Fourth, we analyze available research work related to cross layer allocation/optimization for mmWave communications. Fifth, we make a review of mmWave applications to illustrate how mmWave technology can be employed to satisfy other services. At the end of each section described above, we point out the inadequacy of existing work and identify the future work. Sixth, we present some available resources for mmWave communications, including related books about mmWave, commonly used mmWave frequencies, existing protocols based on mmWave, and experimental platforms. Finally, we have a simple summary and point out several promising future research directions.

Millimeter Wave Communication: A Comprehensive Survey

A systematic approach to designing high frequency and high power oscillators using activity condition is introduced. This method finds the best topology to achieve frequencies close to the fmax of the transistors. It also determines the maximum frequency of oscillation for a fixed circuit topology, considering the quality factor of the passive components. Using this technique, in a 0.13 μm CMOS process, we design and implement 121 GHz and 104 GHz fundamental oscillators with the output power of -3.5 dBm and -2.7 dBm, respectively. Next, we introduce a novel triple-push structure to realize 256 GHz and 482 GHz oscillators. The 256 GHz oscillator was implemented in a 0.13 μm CMOS process and the output power of -17 dBm was measured. The 482 GHz oscillator generates -7.9 dBm (0.16 mW) in a 65 nm CMOS process.

/pdf/high-power-terahertz-and-millimeter-wave-oscillator-design-a-2697zxm3zv.pdf

High Power Terahertz and Millimeter-Wave Oscillator Design: A Systematic Approach

A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm 2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.

A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

A systematic methodology for layout optimization of active devices for millimeter-wave (mm-wave) application is proposed. A hybrid mm-wave modeling technique was developed to extend the validity of the device compact models up to 100 GHz. These methods resulted in the design of a customized 90 nm device layout which yields an extrapolated of 300 GHz from an intrinsic device . The device is incorporated into a low-power 60 GHz amplifier consuming 10.5 mW, providing 12.2 dB of gain, and an output of 4 dBm. An experimental three-stage 104 GHz tuned amplifier has a measured peak gain of 9.3 dB. Finally, a Colpitts oscillator operating at 104 GHz delivers up to 5 dBm of output power while consuming 6.5 mW.

Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS

A customized 90nm device layout yields an extrapolated fmax of 300GHz. The device is incorporated into a low-power 60GHz amplifier consuming 10.5mW, providing 12dB of gain, and an output P1dB of 4dBm. An experimental 3-stage 104GHz amplifier has a measured peak gain of 9.3dB. Finally, a Colpitts oscillator at 104GHz delivers up to -5dBm of output power while consuming 6mW.

Low-Power mm-Wave Components up to 104GHz in 90nm CMOS

30 GHz low noise amplifier was designed and fabricated in a 90 nm digital CMOS process. The mm-wave amplifier has a peak gain of 20 dB at 28.5 GHz and a 3 dB bandwidth of 2.6 GHz with the input and output matching better than 12 dB and 17 dB over the entire band respectively. The NF is 2.9 dB at 28 GHz and less than 4.2 dB across the band and it can deliver 2 dBm of power to a matched load at its 1 dB compression point. The amplifier has a measured linearity of IIIP3=-7.5 dBm. It consumes 16.25 mW of power using a low supply voltage of 1 V and occupies an area (excluding the pads) of 1600 mum x 420 mum.

30 GHz CMOS Low Noise Amplifier

A two-stage 60 GHz 90 nm CMOS PA has been designed and fabricated The amplifier has a measured power gain of 98 dB The input is gain matched while the output is matched to maximize the output power The measured P-1dB = 67 dBm with a corresponding power added efficiency of 20% This amplifier can be used as a pre-driver or as the main PA for short range wireless communication The output power can be boosted with on-chip or spatial power combining

A 60 GHz Power Amplifier in 90nm CMOS Technology

The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption

M. Bohsali

Papers

Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS

Low-Power mm-Wave Components up to 104GHz in 90nm CMOS

30 GHz CMOS Low Noise Amplifier

A 60 GHz Power Amplifier in 90nm CMOS Technology

A 60-GHz 90-nm CMOS cascode amplifier with interstage matching