Recent changes in how people consume multimedia services are causing an explosive increase in mobile traffic. With more and more people using wireless networks, the demand for the ultra-fast wireless communications systems is increasing. To date, this demand has been accommodated with advanced modulation schemes and signal-processing technologies at microwave frequencies. However, without increasing the carrier frequencies for more spectral resources, it may be quite difficult to keep up with the needs of users. Although there are several alternative bands, recent advances in terahertz-wave (THz-wave) technologies have attracted attention due to the huge bandwidth of THz waves and its potential for use in wireless communications. The frequency band of 275 ~ 3000 GHz , which has not been allocated for specific uses yet, is especially of interest for future wireless systems with data rates of 10 Gb/s or higher. Although THz communications is still in a very early stage of development, there have been lots of reports that show its potential. In this review, we will examine the current progress of THz-wave technologies related to communications applications and discuss some issues that need to be considered for the future of THz communications.

Present and Future of Terahertz Communications

This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in today's mainstream CMOS technologies.

Millimeter-wave CMOS design

Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. The interconnect power was also insignificant compared to the transistor power. With uniprocessor designs providing diminishing returns and the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores has become a critical part of the design. Transistor miniaturization has led to high global wire delay, and interconnect power comparable to transistor power. CMP design proposals can no longer ignore the interaction between the memory hierarchy and the interconnection network that connects various elements. This necessitates a detailed and accurate interconnection network model within a full-system evaluation framework. Ignoring the interconnect details might lead to inaccurate results when simulating a CMP architecture. It also becomes important to analyze the impact of interconnection network optimization techniques on full system behavior. In this light, we developed a detailed cycle-accurate interconnection network model (GARNET), inside the GEMS full-system simulation framework. GARNET models a classic five-stage pipelined router with virtual channel (VC) flow control. Microarchitectural details, such as flit-level input buffers, routing logic, allocators and the crossbar switch, are modeled. GARNET, along with GEMS, provides a detailed and accurate memory system timing model. To demonstrate the importance and potential impact of GARNET, we evaluate a shared and private L2 CMP with a realistic state-of-the-art interconnection network against the original GEMS simple network. The objective of the evaluation was to figure out which configuration is better for a particular workload. We show that not modeling the interconnect in detail might lead to an incorrect outcome. We also evaluate Express Virtual Channels (EVCs), an on-chip network flow control proposal, in a full-system fashion. We show that in improving on-chip network latency-throughput, EVCs do lead to better overall system runtime, however, the impact varies widely across applications.

/pdf/garnet-a-detailed-on-chip-network-model-inside-a-full-system-38fe9ifqjr.pdf

GARNET: A detailed on-chip network model inside a full-system simulator

The new theory of compressive sensing enables direct analog-to-information conversion of compressible signals at sub-Nyquist acquisition rates. The authors develop new theory, algorithms, performance bounds, and a prototype implementation for an analog-to-information converter based on random demodulation. The architecture is particularly apropos for wideband signals that are sparse in the time-frequency plane. End-to-end simulations of a complete transistor-level implementation prove the concept under the effect of circuit nonidealities.

/pdf/theory-and-implementation-of-an-analog-to-information-4gq0kr2lqy.pdf

Theory and Implementation of an Analog-to-Information Converter using Random Demodulation

Recent studies showed that conventional approaches being used to solve problems imposed by hard-wired metal interconnects will eventually encounter fundamental limits and may impede the advance of future ultralarge-scale integrated circuits (ULSls). To surpass these fundamental limits, we introduce a novel RF/wireless interconnect concept for future inter- and intra-ULSI communications. Unlike the traditional "passive" metal interconnect, the "active" RF/wireless interconnect is based on low loss and dispersion-free microwave signal transmission, near-field capacitive coupling, and modem multiple-access algorithms. In this paper we address issues relevant to the signal channeling of the RF/wireless interconnect and discuss its advantages in speed, signal integrity, and channel reconfiguration. The electronic overhead required in the RF/wireless-interconnect system and its compatibility with the future ULSI and MCM (multi-chip-module) will be discussed as well.

RF/wireless interconnect for inter- and intra-chip communications

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or -15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N=2k, where k=1,2,3,4,...,n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N=4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

This paper presents a two-way current-combining-based W-band power amplifier (PA) in 65-nm CMOS technology. An analytical model and design method for W-band power combiners are presented, which indicates current combining is preferred for millimeter-wave frequencies due to a good current handling capability, symmetrical design, and low sensitivity to parasitics. To demonstrate the concept, a two-way current-combining-based PA has been fabricated, where each channel utilizes compact and symmetrical transformer-based inter-stage coupling to realize a preferred fully differential implementation. This PA operates from 101 to 117 GHz with maximum power gain of 14.1 dB, saturated output power (Psat) of 14.8 dBm, and peak power-added efficiency of 9.4%. The core chip area without pads is 0.106 mm2.

Two-Way Current-Combining $W$ -Band Power Amplifier in 65-nm CMOS

A 2-GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18-/spl mu/m one-poly six-metal CMOS. A triple-cross connection method is devised to improve the offset averaging efficiency. Circuit techniques, enabling a state-of-the-art figure-of-merit of 3.5 pJ per conversion step, are discussed. The peak DNL and INL are measured as 0.32 LSB and 0.5 LSB, respectively. The SNDR and SFDR have achieved 36 and 48dB, respectively, with 4 MHz input signal. Near Nyquist input frequencies, the SNDR and SFDR maintain above 30 and 35.5dB, respectively, up to 941 MHz. The complete ADC, including front-end track-and-hold amplifiers and clock buffers, consumes 310 mW from a 1.8-V supply while operating at 2-GHz conversion rate. The prototype ADC occupies an active chip area of 0.5 mm/sup 2/.

M.-C.F. Chang

Papers

RF/wireless interconnect for inter- and intra-chip communications

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

Two-Way Current-Combining $W$ -Band Power Amplifier in 65-nm CMOS

A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging