The improvements in the device characteristics of n-channel MOSFET's that occur at low temperatures are considered in this paper. The device parameters for polysilicon gate FET's with channel lengths of the order of 1 µm have been studied both experimentally and theoretically at temperatures ranging from room temperature down to liquid nitrogen temperature. Excellent agreement was found between the experimental dc device characteristics and those predicted by a two-dimensional current transport model, indicating that device behavior is well understood and predictable over this entire temperature range. A device design is presented for an enhancement mode FET with a channel length of I µm that is suitable for operation at liquid nitrogen temperature.

Very small MOSFET's for low-temperature operation

A general review of energy levels in silicon covering information up to about 1972 appears in the book Deep Impurities in Semiconductors by A. G. Milnes (1973). Since that time much new information has been published and the purpose of this chapter is to review this progress. As new experimental techniques have been developed, many of the previously reported energy levels and capture cross sections have been revised, and a number of impurities have been found to exhibit more levels than previously suspected. Also, more has been learned about native defects and irradiation-produced levels in silicon. Deep impurity studies are of importance in connection with process­ induced defects that limit the yield of integrated circuits of increasing size, complexity, and resolution. Also, such defects can be harmful to the performance of large-area discrete devices such as power transistors, thyristors, and solar cells. Interest has continued in silicon extrinsic photoconductors for infrared detection with impurities such as indium, gallium, sulfur, and selenium (see, for example, Loh et al 1977). There has also been progress in the theoretical area, although in general energy levels of deep impurities in silicon still cannot be cal­ culated with any great success. The review begins with a brief look at some theoretical approaches.

Energy Levels in Silicon

This paper reports on a fabrication technique for realizing micro-Si probe arrays with MOSFETs on the same Si substrate. Micro-Si probe arrays have been successfully fabricated on Si (111) substrates by selective vapor-liquid-solid (VLS) growth using catalytic Au dot arrays and Si/sub 2/H/sub 6/ used as the gas source for a molecular-beam-epitaxy. The Si probes can be grown at temperatures ranging from 500/spl deg/C to 700/spl deg/C. In this paper, MOSFETs were fabricated on Si (111) substrates and Au dots were placed at the drain regions of the MOSFETs in order to grow the Si probes. VLS growth at 700/spl deg/C for 2 h was carried out on these substrates. Consequently, the MOSFETs can be used in on-chip circuits for the VLS-Si probe array. The electrical characteristics of the MOSFETs were measured before and after the VLS process. After the VLS process, no changes in the MOSFET characteristics were observed due to the effects of Au-diffusion, and the results confirmed that VLS growth at a temperature of 700/spl deg/C allows fabrication of micro-Si probes without deterioration of the MOSFETs. VLS-Si probes with controlled conductance were realized. The as-grown Si probes were of high resistance, but could be changed to various conductivities by impurity diffusion.

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Selective vapor-liquid-solid epitaxial growth of micro-Si probe electrode arrays with on-chip MOSFETs on Si (111) substrates

The operation of a new type of infrared photon detector is described. This device is a gold-doped n-channel MOSFET that employs impurity photoionization to modulate its drain-to-source conductance. A simple mathematical model is developed whereby the infrared-sensing MOSFET (IRFET) can be analyzed, and experimental results that verify the model are provided. The near-infrared, i.e., wavelengths from 1.38 to 3.54 µm, response of gold impurity centers in the space-charge region behind the strong surface inversion layer of a MOSFET is shown to correspond to the characteristics observed previously by other authors for the gold centers in bulk silicon. A static read-only memory capability and high responsivity, typically 4 mW/µJ, are the most significant IRFET characteristics. Applications in large-scale-integrated imaging arrays are anticipated.

Experimental characterization of gold-doped infrared-sensing MOSFET's

Si MOSFET's on Au-diffused high-resistivity substrates were fabricated and their electrical properties were investigated. At 80 K, the current leakage between the source and drain of both n- and p-channel devices decreased below 10-10A, and the devices exhibited normally-off behaviors. Au concentrations ( N ) in Si substrates as a function of diffusion temperature T diff was determined from the change in the threshold voltage. N versus T diff thus obtained is in fairly good agreement with that obtained by other methods. Dependence of effective mobility on T diff was investigated in the form of a MOS device. The effective mobility decreased with increasing T diff , and it became clear that the diffusion temperature must be lower than about 700°C to obtain semi-insulating substrates with reasonably high carrier mobility. A C-MOS inverter was fabricated using an Au-diffused Si substrate, where no isolation wells were needed, in operation at low temperatures.

MOSFET's on Au-diffused high-resistivity Si substrates

The temperature dependence of the turn-on voltage of gold-doped and control n- and p-channel MOSFETs has been measured. To account for the large positive shift of turn-on voltage, V T Au , of gold treated n- and p-channel devices, it has been proposed that the gold eliminates the fast interface traps of continuous energy distribution, and that additional acceptor states very close to the valence band can cause additional charge Q A Au , which can dominate the effect of acceptor and donor levels of gold ions in the silicon surface space charge region, and can also over-compensate the surface state charge, Q ss . To fit the theoretical V T Au versus T curve to experimental curves, an accumulation of electrically active gold within the surface space charge region has been considered in n-channel devices and depletion in p-channel devices.

M.E. Sproul

Papers

Temperature dependence of turn-on voltage of gold-doped MOSFETs