M
M. Hatzimihail
Researcher at University of Piraeus
Publications - 4
Citations - 190
M. Hatzimihail is an academic researcher from University of Piraeus. The author has contributed to research in topics: Reduced instruction set computing & Fault coverage. The author has an hindex of 4, co-authored 4 publications receiving 178 citations.
Papers
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Journal ArticleDOI
Systematic Software-Based Self-Test for Pipelined Processors
Dimitris Gizopoulos,Mihalis Psarakis,M. Hatzimihail,Michail Maniatakos,Antonis Paschalis,Anand Raghunathan,Srivaths Ravi +6 more
TL;DR: A systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic, and applies it to two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model.
Proceedings ArticleDOI
A methodology for detecting performance faults in microprocessors via performance monitoring hardware
TL;DR: This paper investigates the effects of performance faults in speculative execution units and proposes a generic, software-based test methodology, which utilizes available processor resources: hardware performance monitors and processor exceptions, to detect these faults in a systematic way.
Journal ArticleDOI
An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set
Ioannis Voyiatzis,Antonis Paschalis,Dimitris Gizopoulos,Constantin Halatsis,Frosso S. Makri,M. Hatzimihail +5 more
TL;DR: The proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing and can be equally well utilized for manufacturing and concurrent on-lineTesting in the field.
Proceedings ArticleDOI
Software-based self-test for pipelined processors: a case study
TL;DR: This paper demonstrates for first time the full applicability of a recently proposed SBST methodology to a publicly available complex RISC processor implementation which includes a full pipelined architecture consisting of five pipeline stages, hazard detection, data forwarding and exceptions handling.