M
M. Igeta
Publications - 2
Citations - 208
M. Igeta is an academic researcher. The author has contributed to research in topics: Double data rate & Redundancy (engineering). The author has an hindex of 2, co-authored 2 publications receiving 208 citations.
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Journal ArticleDOI
A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay
Takanori Saeki,Y. Nakaoka,Mamoru Fujita,Akio Tanaka,Kyoichi Nagata,K. Sakakibara,Tatsuya Matano,Y. Hoshino,K. Miyano,S. Isa,S. Nakazawa,E. Kakehashi,J.M. Drynan,M. Komuro,T. Fukase,Haruo Iwasaki,M. Takenaka,J. Sekine,M. Igeta,N. Nakanishi,Toshiro Itani,I. Yoshida,K. Yoshino,S. Hashimoto,Tsuyoshi Yoshii,M. Ichinose,T. Imura,M. Uziie,S. Kikuchi,K. Koyama,Yukio Fukuzo,T. Okuda +31 more
TL;DR: A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.
Journal ArticleDOI
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme
Y. Takai,Mamoru Fujita,Kyoichi Nagata,S. Isa,S. Nakazawa,A. Hirobe,H. Ohkubo,Masato Sakao,S. Horiba,T. Fukase,Y. Takaishi,M. Matsuo,M. Komuro,T. Uchida,T. Sakoh,K. Saino,S. Uchiyama,Y. Takada,J. Sekine,N. Nakanishi,T. Oikawa,M. Igeta,H. Tanabe,Hidenobu Miyamoto,T. Hashimoto,H. Yamaguchi,K. Koyama,Y. Kobayashi,T. Okuda +28 more
TL;DR: This paper describes three circuit technologies indispensable for high-bandwidth multibank DRAM's that achieved a 250-Mb/s/pin, 8-bank, 1-Gb double-data-rate synchronous DRAM.