Memory isolation is a key property of a reliable and secure computing system--an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors

/pdf/flipping-bits-in-memory-without-accessing-them-an-3dirvwezou.pdf

Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations.
We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space.
Our DPGA, a fine-grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite-state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds.
Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20$\times$ the computational density of conventional processors.
Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

Reconfigurable Architectures for General-Purpose Computing

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.

Shallow trench isolation process

A 50-nW standby power compound semiconductor tunneling-based static random access memory SRAM (TSRAM) cell is demonstrated by combining ultralow current-density resonant-tunneling diodes (RTDs) and heterostructure field-effect transistors (HFETs) in one integrated process on an InP substrate. This power represents over two orders of magnitude improvement over previous III-V static memory cells. By increasing the number of vertically integrated RTD's we obtain a 100 nW tri-state memory cell. The cell concept applies to any material system in which low current-density negative differential resistance devices are available.

RTD/HFET low standby power SRAM gain cell

In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.

Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

Novel memory cell technologies for 2.0-V cell operation of 16-Mb SRAMs (static RAMs) have been developed. These technologies have realized 7.2- mu m/sup 2/ cell size, 4.4 effective cell ratio for high noise immunity, and 10/sup 13/-A/cell leakage current. The key features of these technologies include: (1) a symmetrical cell configuration; (2) an access transistor with an N/sup -/ offset resistor; (3) a ground plate expanded on the cell area; and (4) a poly Si TFT (thin film transistor) with an LDO (lightly doped offset) structure, all of which are based on a 0.4- mu m design rule using a SAC (self aligned contact) process. The access transistor with an N/sup -/ offset resistor increases the cell ratio without expanding cell size. The symmetrical cell configuration, the ground plate, and the TFT with the LDO structure contribute to cell operation stability. >

http://ieeexplore.ieee.org/iel5/606/6055/00235351.pdf

16 Mbit SRAM cell technologies for 2.0 V operation

The authors describe a 16 Mbit (2 M*8) SRAM with a 12-ns access time using a 0.4- mu m quadruple-polysilicon, double-metal CMOS technology with TFT (thin-film transistor) load memory cells. An access time of 12 ns is obtained with an optimized rotated memory cell array layout and a read bus midlevel voltage preset scheme (RBMIPS). An on-chip test circuit is included for efficient testing. The test circuit has three modes: redundant rows test, redundant columns test, and 16-bit parallel test. >

A 3.3-V 12-ns 16-Mb CMOS SRAM

This paper describes three circuit technologies indispensable for high-bandwidth multibank DRAM's. (1) A clock generator based on a bidirectional delay (BDD) eliminates the output skew. The BDD measures the cycle time as the quantity charged or discharged of an analog quantity, and replicates it in the next cycle. This achieves a 0.18-mm/sup 2/, two-cycle-lock clock generator operating from 25 to 167 MHz with a 30-ps resolution. (2) A quad-coupled receiver eliminates the internal skew caused by the difference between a rise input and a fall input by 40%. (3) An interbank shared redundancy scheme (ISR) with a variable unit redundancy (VUR) efficiently increases yield in multibank DRAM's. The ISR allows redundancy match circuits to be shared with two or more banks. The VUR allows the number of units replaced to be variable. These circuit technologies achieved a 250-Mb/s/pin, 8-bank, 1-Gb double-data-rate synchronous DRAM.

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

This is the first detailed study of data retention characteristics of DRAM with bias ECR-CVD oxide-filled shallow trench isolation (STI). It clarifies the relationship between trench sidewall stress and data retention characteristics. Excessive stress on trench sidewalls causes strain and defect-related leakage current, and it degrades data retention time. Strain and defects are introduced by process conditions like deep trenching, high-temperature densification, and vertically etched trenching in bias ECR-CVD oxide-filled trench case. By eliminating the cause of leakage current, fully operating 0.18 /spl mu/m-rule DRAMs have been manufactured.

S. Horiba

Papers

Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

16 Mbit SRAM cell technologies for 2.0 V operation

A 3.3-V 12-ns 16-Mb CMOS SRAM

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time