This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution /spl Sigma//spl Delta/ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-/spl mu/m double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply.

A 2.5-V sigma-delta modulator for broadband communications applications

High-speed high-resolution /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR) However, lowering the OSR limits the efficiency of a /spl Delta//spl Sigma/ ADC in achieving a high-resolution A/D conversion This paper presents several techniques that enable the OSR reduction in /spl Delta//spl Sigma/ ADCs without compromising the resolution 1) Noise transfer function (NTF) In this paper, a single-stage multibit /spl Delta//spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities Its performance is validated through behavioral simulations and compared to traditional /spl Delta//spl Sigma/ modulator structures 2) Signal transfer function (STF) This paper describes how the STF of a /spl Delta//spl Sigma/ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation 3) Dynamic element matching (DEM) is also presented Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit /spl Delta//spl Sigma/ modulator, especially when the number of DAC elements is large However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio Its implementation adds no extra delay in the /spl Delta//spl Sigma/ feedback loop and requires only minimal additional digital hardware Existing schemes for DWA tone reduction are also compared

High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling /spl Delta//spl Sigma/ ADCs for broad-band applications

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-/spl mu/m CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm/sup 2/. Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance.

A wideband CMOS sigma-delta modulator with incremental data weighted averaging

High-speed high-resolution analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR). However, lowering the OSR limits the efficiency of a ADC in achieving a high-resolution A/D conversion. This paper presents several techniques that enable the OSR reduction in ADCs without compromising the resolution. 1) Noise transfer function (NTF). In this paper, a single-stage multibit modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs. Its key fea- tures include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities. Its performance is validated through behavioral simulations and compared to traditional mod- ulator structures. 2) Signal transfer function (STF). This paper describes how the STF of a modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation. 3) Dynamic element matching (DEM) is also presented. Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit modulator, especially when the number of DAC elements is large. However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range. This paper proposes a simple technique, called Pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio. Its implementation adds no extra delay in the feedback loop and requires only minimal additional digital hardware. Existing schemes for DWA tone reduction are also compared.

High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 22-MS/s sigma-delta analog-to-digital converter (ADC) The analog modulator and digital decimator sections were implemented in a 035 /spl mu/m CMOS double-poly triple-level metal 33-V process The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation Both modulators employ a cascade sigma-delta topology The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections

/pdf/14-bit-2-2-ms-s-sigma-delta-adc-s-4mzkbzhqch.pdf

14-bit 2.2-MS/s sigma-delta ADC's

Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded /spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.

/pdf/sndr-sensitivity-analysis-for-cascaded-spl-sigma-spl-delta-28bc7hq1n7.pdf

SNDR sensitivity analysis for cascaded /spl Sigma//spl Delta/ modulators

This paper presents the design and test results of a 4th and 6th order, 14-bit, 22MS/s sigma-delta ADC The analog modulator and digital decimator sections were implemented in a 35µM CMOS, double poly, triple level metal 33v process The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation

http://ieeexplore.ieee.org/iel5/9918/31527/01471101.pdf

M. Ishiwaki

Papers

14-bit 2.2-MS/s sigma-delta ADC's

SNDR sensitivity analysis for cascaded /spl Sigma//spl Delta/ modulators

14–bit, 2.2MS/s sigma delta ADCs

M. Ishiwaki

Papers

14-bit 2.2-MS/s sigma-delta ADC's

SNDR sensitivity analysis for cascaded /spl Sigma//spl Delta/ modulators

14&#8211;bit, 2.2MS/s sigma delta ADCs

14–bit, 2.2MS/s sigma delta ADCs